SH7721 datasheet(108/1524 Pages) RENESAS

108 / 1524 page

Section 2

CPU

Rev. 3.00 Jan. 18, 2008 Page 46 of 1458

REJ09B0033-0300

R0*1,*2

R1*2

R2*2

R3*2

R4*2

R5*2

R6*2

R7*2

R10

R11

R12

R13

R14

R15

General Registers: Undefined after reset

Notes: 1. R0 functions as an index register in the indexed

GBR-indirect addressing mode. In some

instructions, only R0 can be used as the source

or destination register.

2. R0 to R7 are banked registers. In privileged

mode, either R0_BANK0 to R7_BANK0 or

R0_BANK1 to R7_BANK1 is selected by the

RB bit in the SR register.

Figure 2.4

General Registers

2.3.2

System Registers

The system registers: multiply and accumulate registers (MACH/MACL) and procedure register

(PR) as system registers can be accessed by the LDS and STS instructions.

(1)

Multiply and Accumulate Registers (MACH/MACL)

The multiply and accumulate registers (MACH/MACL) store the results of multiplication and

accumulation instructions or multiplication instructions. The MACH/MACL registers also store

addition values for the multiplication and accumulations. After reset, these registers are undefined.

The MACH and MACL registers store upper 32 bits and lower 32 bits, respectively.

(2)

Procedure Register (PR)

The procedure register (PR) stores the return address for a subroutine call using the BSR, BSRF,

or JSR instruction. The return address stored in the PR register is restored to the program counter

(PC) by the RTS (return from the subroutine) instruction. After reset, this register is undefined.

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