PCA85133USLASH2DASLASHQ1 datasheet(18/44 Pages) NXP

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PCA85133_1

Product data sheet

Rev. 1 — 23 October 2009

18 of 44

NXP Semiconductors

PCA85133

Universal LCD driver for low multiplex rates

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. By means of the output bank selector, the displayed RAM

banks are exchanged with alternate RAM banks at the blink frequency. This mode can

also be speciﬁed by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can blink by selectively changing the display RAM data at ﬁxed time

intervals.

If the entire display can blink at a frequency other then the typical blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 10).

7.16 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

By connecting pin SDAACK to pin SDA on the PCA85133, the SDA line becomes fully

I2C-bus compatible. In COG applications where the track resistance from the SDAACK pin

to the system SDA line can be signiﬁcant, possibly a voltage divider is generated by the

bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a consequence it

may be possible that the acknowledge generated by the PCA85133 can’t be interpreted

as logic 0 by the master. In COG applications where the acknowledge cycle is required, it

is therefore necessary to minimize the track resistance from the SDAACK pin to the

system SDA line to guarantee a valid LOW level.

By separating the acknowledge output from the serial data line (having the SDAACK open

circuit) design efforts to generate a valid acknowledge level can be avoided. However, in

that case the I2C-bus master has to be set up in such a way that it ignores the

acknowledge cycle.2

The following deﬁnition assumes SDA and SDAACK are connected and refers to the pair

as SDA.

Table 7.

Blink frequencies

Blink mode

Operating mode ratio

Blink frequency with respect to fclk (typical)

Unit

fclk = 1.970 kHz

fclk = 2.640 kHz

off

blinking off

2.5

3.5

1.3

1.7

0.6

0.9

clk

768

---------

clk

1536

------------

clk

3072

------------

For further information, please consider the NXP application note: Ref. 1 “AN10170”.

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