PCA85133USLASH2DASLASHQ1 datasheet(30/44 Pages) NXP

30 / 44 page

PCA85133_1

Product data sheet

Rev. 1 — 23 October 2009

30 of 44

NXP Semiconductors

PCA85133

Universal LCD driver for low multiplex rates

12. Application information

12.1 Cascaded operation

In large display conﬁgurations up to 16 PCA85133 can be recognized on the same

I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable

I2C-bus slave address (SA0).

When cascaded PCA85133 are synchronized, they can share the backplane signals from

one of the devices in the cascade. Such an arrangement is cost-effective in large LCD

applications since the backplane outputs of only one device need to be through-plated to

the backplane electrodes of the display. The other PCA85133 of the cascade contribute

additional segment outputs, but their backplane outputs are left open-circuit

(see Figure 20).

Table 18.

Addressing cascaded PCA85133

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

100000

0011

0102

0113

1004

1015

1106

1117

210008

0019

01010

01111

10012

10113

11014

11115

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