PCA85133USLASH2DASLASHQ1 datasheet(4/44 Pages) NXP

4 / 44 page

PCA85133_1

Product data sheet

Rev. 1 — 23 October 2009

4 of 44

NXP Semiconductors

PCA85133

Universal LCD driver for low multiplex rates

Pinning information

6.1 Pinning

6.2 Pin description

[1]

The substrate (rear side of the die) is wired to VSS but should not be electrically contacted.

Viewed from active side. For mechanical details, see Figure 23.

Fig 2.

Pin conﬁguration of PCA85133

013aaa045

PCA85133

Table 3.

Pin description overview

Symbol

Description

SDAACK

1 to 3

I2C-bus acknowledge output

SDA

4 to 6

I2C-bus serial data input

SCL

7 to 9

I2C-bus serial clock input

CLK

clock input and output

VDD

11 to 13

supply voltage

SYNC

cascade synchronization input and output

OSC

oscillator select

frame frequency select

A0, A1 and A2

17 to 19

subaddress input

SA0

I2C-bus slave address input

VSS[1]

21 to 23

ground supply voltage

VLCD

24 to 26

LCD supply voltage

BP2, BP0, BP3 and BP1

27, 28, 109 and 110

LCD backplane output

S0 to S79

29 to 108

LCD segment output

D1 to D9

dummy pins

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