| Electronic Components Datasheet Search |
|
PCA85133U/2DA/Q1 Datasheet(PDF) 32 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCA85133U/2DA/Q1 Datasheet(HTML) 32 Page - NXP Semiconductors |
|
32 / 44 page ![]() PCA85133_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 1 — 23 October 2009 32 of 44 NXP Semiconductors PCA85133 Universal LCD driver for low multiplex rates The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, then the device will not be able to synchronize properly. This is particularly applicable to COG applications. Table 19 shows the limiting values for contact resistance. Fig 21. Synchronization of the cascade for the various PCA85133 drive modes Table 19. SYNC contact resistance Number of devices Maximum contact resistance 2 6000 Ω 3 to 5 2200 Ω 6 to 10 1200 Ω 11 to 16 700 Ω Tfr = f fr 1 BP0 SYNC BP0 (1/2 bias) SYNC BP0 (1/3 bias) (a) static drive mode. (b) 1:2 multiplex drive mode. (c) 1:3 multiplex drive mode. (d) 1:4 multiplex drive mode. BP0 (1/3 bias) SYNC SYNC BP0 (1/3 bias) mgl755 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |