DAC7678SPW datasheet(35/52 Pages) TI

35 / 52 page

DAC7678

www.ti.com

SBAS493A – FEBRUARY 2010 – REVISED AUGUST 2010

POWER-ON RESET TO ZERO-SCALE OR

Alternatively, all DAC outputs can be updated

MID-SCALE

simultaneously using the built-in LDAC software

function. The LDAC register offers additional flexibility

The DAC7678 contains a power-on reset (POR)

and control, giving the ability to select which DAC

circuit

that

controls

the

output

voltage

during

channel(s) should be updated simultaneously when

power-on.

For

devices

housed

the

TSSOP

the hardware LDAC pin is being brought low. The

package, at power-on, all DAC registers are filled with

LDAC register is loaded with an 8-bit word (DB15 to

zeros and the output voltages of all DAC channels

DB8) using control bits C3, C2, C1, and C0. The

are set to zero-scale. For devices housed in the QFN

default value for each bit, and therefore each DAC

package, all DAC registers are set to have all DAC

channel, is zero and the external LDAC pin operates

channels power on depending of the state of the

in normal mode. If the LDAC register bit for a

RSTSEL pin.

selected DAC channel is set to '1', that DAC channel

ignores the external LDAC pin and updates only

The RSTSEL pin value is read at power-on and

through the software LDAC command. If, however,

should be set prior to or simultaneously with AVDD.

the LDAC register bit is set to '0', the DAC channel is

For RSTSEL set to AVDD, the DAC channels are

controlled by the external LDAC pin.

loaded with midscale code. If RSTSEL is set to

ground, the DAC channels are loaded with zero-scale

This

combination

software

and

hardware

code. All DAC channels remain in this state until a

simultaneous update function is particularly useful in

valid write sequence and load command are sent to

applications where only selective DAC channels are

the respective DAC channel. The power-on reset

to be updated simultaneously, while keeping the other

function is useful in applications where it is important

channels unaffected and updating those channels

to know the output state of each DAC while the

synchronously.

device is in the process of powering on.

The internal reference is powered off/down by default,

POWER-DOWN MODES

and remains that way until a valid reference-change

The DAC7678 has two separate sets of power-down

command is executed.

commands. One set is for the DAC channels and the

other set is for the internal reference. For more

LDAC FUNCTIONALITY

information on powering down the reference see the

Enable/Disable Internal Reference section.

The DAC7678 offers both software and hardware

simultaneous updates and control functions. The

DAC Power-Down Commands

DAC double-buffered architecture is designed so that

new data can be entered for each DAC without

The DAC7678 uses four modes of operation. These

disturbing the analog outputs.

modes are accessed by using control bits C3, C2,

C1, and C0. The control bits must be set to '0100'.

The DAC7678 data updates can be performed either

When the control bits are set correctly, the four

in synchronous or asynchronous mode.

different

power-down

modes

are

software

In synchronous mode, data are updated on the falling

programmable by setting bits PD0 (DB13) and PD1

edge of the acknowledge signal that follows LSDB.

(DB14) in the control register. Table 19 shows how to

For synchronous mode updates, the LDAC pin is not

control the operating mode with data bits PD0 (DB13)

required

and

must

connected

GND

and

PD1

(DB14).

The

DAC7678

treats

the

permanently.

power-down condition as data; all the operational

modes are still valid for power down. It is possible to

In asynchronous mode, the LDAC pin is used as a

broadcast

power-down

condition

all

the

negative-edge-triggered

timing

signal

for

DAC7678s in a system. It is also possible to

asynchronous DAC updates. Multiple single-channel

power-down a channel and update data on other

updates can be performed in order to set different

channels. Furthermore, it is possible to write to the

channel buffers to desired values and then make a

DAC register/buffer of the DAC channel that is

falling edge on the LDAC pin. The data buffers of all

powered down. When the DAC channel is then

the channels must be loaded with the desired data

powered on, it will contain this new value.

before an LDAC falling edge. After a high-to-low

LDAC

transition,

all

DACs

are

simultaneously

When both the PD0 and PD1 bits are set to '0', the

updated with the last contents of the corresponding

device works normally with its typical consumption of

data buffers. If the contents of a data buffer are not

1.49 mA at 5.5V. The reference is included with the

changed by the serial interface, the corresponding

operation of all eight channels. However, for the three

DAC output remains unchanged after the LDAC

power-down modes, the supply current falls to 0.42

trigger.

µA at 5.5V (0.25 µA at 2.7V). Not only does the

supply current fall, but the output stage also switches

internally from the output amplifier to a resistor

network of known values as shown in Figure 93.

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