DAC7678SPW datasheet(26/52 Pages) TI

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NotAcknowledge

Acknowledge

ClockPulsefor

Acknowledgement

START

Condition

DataOutput

byTransmitter

DataOutput

byReceiver

SCLfrom

Master

Start

Condition

SDA

Stop

Condition

SDA

SCL

DAC7678

SBAS493A – FEBRUARY 2010 – REVISED AUGUST 2010

www.ti.com

TWO-WIRE, I

2C-COMPATIBLE INTERFACE

and fast modes. The protocol for high-speed mode is

different from the F/S-mode, and it is referred to as

The I2C™ is a 2-wire serial interface developed by

HS-mode. The DAC7678 supports 7-bit addressing.

Philips Semiconductor (see I2C™-Bus Specification,

The 10-bit addressing and general call address are

Rev. 03, June 2007). The bus consists of a data line

not supported.

(SDA) and a clock line (SCL) with pull-up structures.

When the bus is idle, both SDA and SCL lines are

Other than specific timing signals, the I2C interface

pulled high. All the I2C™ compatible devices connect

works with serial bytes. At the end of each byte, a 9th

to the I2C™ bus through open drain I/O pins, SDA

clock

cycle

used

generate/detect

and SCL.

acknowledge signal, Acknowledge is when the SDA

line is pulled low during the high period of the 9th

The I2C specification states that the device that

clock cycle. A not-acknowledge is when the SDA line

controls communication is called a master, and the

is left high during the high period of the 9th clock

devices that are controlled by the master are called

cycle as shown in Figure 90.

slaves. The master device generates the SCL signal.

The master device also generates special timing

conditions (start condition, repeated start condition,

and stop condition) on the bus to indicate the start or

stop of a data transfer. Device addressing is also

done by the master. The master device on an I2C bus

is usually a microcontroller or a digital signal

processor (DSP). The DAC7678 on the other hand,

operates as a slave device on the I2C bus. A slave

devcie acknowledges master's commands and upon

master's control, either receives or transmits data.

Figure 90. Acknowledge and Not Acknowledge

on the I2C Bus

F/S Mode Protocol

•

The master initiates data transfer by generating a

start condition. The start condition is when a

high-to-low transition occcurs on the SDA line

while SCL is high, as shown in Figure 90. All

Figure 89. Start and Stop Conditions

I2C-compatible

devices

recognize

start

condition.

The DAC7678 normally operates as a slave receiver.

•

The master then generates the SCL pulses, and

A master device writes to the DAC7678, a slave

transmits the 7-bit address and the read/write

receiver. However, if a master device inquires the

direction bit (R/W) on the SDA line. During all

DAC7678

internal

data,

the

DAC7678

transmissions, the master ensures that data is

operates as a slave transmitter. In this case, the

valid. A valid data condition requires the SDA line

master device reads from the DAC7678, a slave

to be stable during the entire high period of the

transmitter. According to I2C™ terminology, read and

clock pulse, as shown in Figure 91. All devices

write are with respect to the master device.

recognize the address sent by the master and

The DAC7678 works as a slave and supports the

compare it to their internal fixed addresses. Only

following data transfer modes, as defined in the I2C™

the

slave

device

with

matching

address

-Bus Specification:

generates an acknowledge by pulling the SDA line

•

Standard mode (100 kbps)

low during the entire high period of the ninth SCL

cycle, as shown in Figure 90 by pulling the SDA

•

Fast mode (400 kbps)

line low during the entire high period of the 9th

•

Fast mode+ (1.0Mbps) and

SCL cycle. Upon detecting this acknowledge, the

•

High-Speed mode (3.4 Mbps)

master knows the communication link with a slave

has been established.

The data transfer protocol for standard and fast

modes is exactly the same, therefore they are

•

The master generates further SCL cycles to either

referred to as F/S-mode in this document. The fast

transmit data to the slave (R/W bit 0) or receive

mode+ protocol is supported in terms of data transfer

data from the slave (R/W bit 1). In either case, the

speed but not output current. The low-level output

receiver needs to acknowledge the data sent by

current would be 3mA similar to the case of standard

the transmitter. So the acknowledge signal can

either be generated by the master or by the slave,

depending on which one is the receiver. The 9-bit

valid data sequences, consisting of 8-data bits

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