DAC7678SPW datasheet(27/52 Pages) TI

27 / 52 page

ChangeofDataAllowed

DataLineStable;

DataValid

SDA

SCL

Generate ACKNOWLEDGE

Signal

Acknowledgement

Signal From Slave

SDA

SCL

MSB

START or

REPEATED START

Condition

Clock Line Held Low While

Interrupts are Serviced

ACK

3 - 8

ACK

Address

R/W

Recognize START or

REPEATED START

Condition

REPEATED START

STOP

Condition

Recognize STOP or

REPEATED START

Condition

DAC7678

www.ti.com

SBAS493A – FEBRUARY 2010 – REVISED AUGUST 2010

and 1-bit acknowledge can continue as long as

all devices must recognize it and switch their

necessary.

internal setting to support 3.4Mbps operation.

•

To signal the end of the data transfer, the master

•

The master then generates a repeated start

generates a stop condition by pulling the SDA line

condition (a repeated start condition has the same

from low to high while the SCL line is high (see

timing as the start condition). After this repeated

Figure 89). This action releases the bus and stops

start condition, the protocol is the same as

the communication link with the addressed slave.

F/S-mode, except that transmission speeds up to

All I2C-compatible devices recognize the stop

3.4Mbps are allowed. A stop condition ends HS

condition. Upon receipt of a stop condition, the

mode and switches all the internal settings of the

bus is released, and all slave devices then wait for

slave devices to support F/S-mode. Instead of

a start condition followed by a matching address.

using a stop condition, repeated start conditions

should be used to secure the bus in H/S-mode.

DAC7678 I

2C UPDATE SEQUENCE

For a single update, the DAC7678 requires a start

condition, a valid I2C address, a command and

access (CA) byte, and two data bytes, the most

significant data byte (MSDB) and least significant

data byte (LSDB), as shown in Table 7.

Figure 91. Bit Transfer on the I2C Bus

After

each

byte

received,

the

DAC7678

acknowledges by pulling the SDA line low during the

HS Mode Protocol

high period of a single clock pulse, as shown in

Figure 92. These four bytes and acknowledge cycles

•

When the bus is idle, both the SDA and SCL lines

make up the 36 clock cycles required for a single

are pulled high by the pull-up resistors.

update to occur. A valid I2C address selects the

•

The master generates a start condition followed

DAC7678.

by a valid serial byte containing H/S master code

00001XXX. This transmission is made in F/S

mode at no more than 1.0 Mbps. No device is

allowed to acknowledge the H/S master code, but

Figure 92. I2C Bus Protocol

Submit Documentation Feedback

Product Folder Link(s): DAC7678

DAC7678SPW Datasheet(PDF) 27 Page - Texas Instruments

DAC7678SPW Datasheet(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL