DAC7678SPW datasheet(36/52 Pages) TI

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Amplifier

Resistor

String

DAC

Power-Down

Circuitry

Resistor

Network

OUT

DAC7678

SBAS493A – FEBRUARY 2010 – REVISED AUGUST 2010

www.ti.com

The advantage of this switching is that the output

CLEAR CODE REGISTER AND CLR PIN

impedance of the device is known while it is in

The DAC7678 contains a clear code register. The

power-down mode. As described in Table 19, there

clear code register can be accessed via the serial

are three different power-down options. VOUT can be

interface (I2C) and is user configurable. Bringing the

connected internally to GND through a 1k

Ω resistor, a

CLR pin low clears the contents of all DAC registers

100k

Ω resistor, or open-circuited (High-Z). In other

and all DAC buffers and replaces the code with the

words, C3, C2, C1, and C0 = '0100' and DB14 and

code determined by the clear code register. The clear

DB13 = '11' represent a power-down condition with

code register can be written to by applying the

High-Z output impedance for a selected channel.

commands shown in Table 17. The default setting of

DB14 and DB13 = '01' represents a power-down

the clear code register sets the output of all DAC

condition

with

Ω output impedance and '10'

channels to 0V when the CLR pin is brought low. The

represents a power-down condition with 100k

CLR pin is falling-edge triggered; therefore, the

output impedance.

device exits clear code mode on the falling edge of

the acknowledge signal that follows LSDB of the next

Table 19. DAC Operating Modes

write sequence. If the CLR pin is executed (brought

PD1

PD0

low) during a write sequence, this write sequence is

DAC OPERATING MODES

(DB14)

(DB13)

aborted and the DAC registers and DAC buffers are

Power on selected DACs

cleared as described above.

Power down selected DACs, 1k

Ω to GND

When performing a software reset of the device, the

Power down selected DACs, 100k

Ω to GND

clear code register is reset to the default mode (DB5

Power down selected DACs, High-Z to GND

= '0', DB4 = '0'). Setting the clear code register to

DB4 = '1' and DB5 = '1' ignores any activity on the

SPACER

external CLR pin.

SOFTWARE RESET FUNCTION

The DAC7678 contains a software reset feature.

When the software reset feature is executed, the

device (all DAC channels) are reset to the power-on

reset code. All registers inside the device are reset to

the respective default settings. The DAC7678 has an

additional feature of switching straight to high speed

mode after reset. Table 20 shows all the different

modes of the software reset function.

Table 20. Software Reset Modes

DB15

DB14

OPERATING MODES

Figure 93. Output Stage During Power-Down

Default Software reset. Equivalent to

Power-on-Reset

Software reset and set part in High Speed

SPACER

Mode

Software reset and maintain High Speed

Mode state

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