R5F3640ECNFB datasheet(14/91 Pages) RENESAS

14 / 91 page

R01DS0016EJ0100 Rev.1.00

Page 14 of 88

Feb 07, 2011

M16C/64C Group

2. Central Processing Unit (CPU)

Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a

Figure 2.1

CPU Registers

R0H (upper bits of R0)

b15

b8 b7

INTBH

USP

ISP

Note:

1. These registers compose a register bank. There are two register banks.

IPL

b31

b19

INTBL

b15

INTBH is the 4 upper bits of the INTB register and INTBL

is the 16 lower bits.

b19

b15

FLG

b15

Data registers (1)

Address registers (1)

Frame base registers (1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

R1H (upper bits of R1)

R0L (lower bits of R0)

R1L (lower bits of R1)

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