PIC16C765SLASHP datasheet(139/158 Pages) MICROCHIP

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DS41124A-page 139

PIC16C745/765

FIGURE 16-13: A/D CONVERSION TIMING

TABLE 16-11: A/D CONVERSION REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130

TAD

A/D clock period

1.6

——

µsTOSC based, VREF ≥ 3.0V

2.0

—

µsTOSC based,

2.5V

≤ VREF ≤ 5.5V

2.0

4.0

6.0

µs

A/D RC Mode

3.0

6.0

9.0

µs

A/D RC Mode

131

TCNV

Conversion time (not including S/H time)

(Note 1)

—

TAD

132

TACQ

Acquisition time

—

µs

The minimum time is the ampli-

fier settling time. This may be

used if the “new” input voltage

has not changed by more than 1

LSb (i.e., 20.0 mV @ 5.12V)

from the last sampled voltage

(as stated on CHOLD).

134

TGO

Q4 to A/D clock start

—

TOSC/2

—

If the A/D clock source is

selected as RC, a time of TCY is

added before the A/D clock

starts. This allows the SLEEP

instruction to be executed.

135

TSWC

Switching from convert

→ sample time

1.5 §

—

TAD

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:

ADRES register may be read on the following TCY cycle.

See Section 12.1 for min conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2) (1)

432

Note:

If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

1 TCY

134

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