SM89516B datasheet(38/49 Pages) SYNCMOS

38 / 49 page

SM89516B

8-Bit Micro-controller

64KB Flash

& 1KB RAM embedded

Specifications subject to change without notice contact your sales representatives for the most recent information.

ISSFD-M087

Ver D SM89516B 08/07/2015

- 38 -

Interrupt

The SM89516B provides 7 interrupt sources with two priority levels. Each source has its own request flag(s)

located in a special function register. Each interrupt requested by the corresponding flag could individually be

enabled or disabled by the enable bits in SFR’s IE.

When the interrupt occurs, the engine will vector to the predetermined address as given in Table 9-1. Once

interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is

terminated by a return from instruction RETI. When an RETI is performed, the processor will return to the

instruction that would have been next when interrupt occurred.

When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set

regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle,

and then samples are polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled,

then interrupt request flag is set. On the next instruction cycle the interrupt will be acknowledged by hardware

forcing an LCALL to appropriate vector address.

Interrupt response will require a varying amount of time depending on the state of microcontroller when the

interrupt occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt

will not be invoked. In other cases, the response time depends on current instruction.

Table 9-1: Interrupt vectors

Priority

level

Interrupt Request Flags

Interrupt Vector

Address

Interrupt Number

*(use Keil C Tool)

1 (highest)

IE0 – External interrupt 0

0003h

TF0 – Timer 0 interrupt

000Bh

IE1 – External interrupt 1

0013h

TF1 – Timer 1 interrupt

001Bh

RI/TI – Serial channel interrupt

0023h

TF2/EXF2 – Timer 2 interrupt

002Bh

Two Wire Serial Interface

003Bh

*See Keil C about C51 User’s Guide about Interrupt Function description

Mnemonic

Description

Dir.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RST

Interrupt

Interrupt Enable

A8H

ET2

ET1

EX1

ET0

EX0

00H

IE1

Interrupt Enable

A9H

ETWSI

00H

Interrupt Priority

B8H

PT2

PT1

PX1

PT0

PX0

00H

IP1

Interrupt Priority

B9H

PTWSI

00H

Mnemonic: IE

Address: A8h

Reset

ET2

ET1

EX1

ET0

EX0

00h

EA: EA=0 – Disable all interrupt.

EA=1 – Enable all interrupt.

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