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SM89516B Datasheet(PDF) 47 Page - SyncMOS Technologies,Inc

Part # SM89516B
Description  On-chip 768 bytes expanded RAM
PDF  49 Pages
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Manufacturer  SYNCMOS [SyncMOS Technologies,Inc]
Direct Link  http://www.syncmos.com.tw
Logo SYNCMOS - SyncMOS Technologies,Inc

SM89516B Datasheet(HTML) 47 Page - SyncMOS Technologies,Inc

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SM89516B
8-Bit Micro-controller
64KB Flash
& 1KB RAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M087
Ver D SM89516B 08/07/2015
- 47 -
signal has been received after the complete 8-bit data transmit on the bus.
(Read only)
MST: Set 1 to force working at TWSI master mode.
TXACK: The acknowledge bit for response to transmitter or master addressing. When
receiving complete 8-bit data, setting this bit to respond with NACK otherwise
ACK is responded.
Mnemonic: TWSIA
Address: C1h
7
6
5
4
3
2
1
0
Reset
ADR.6
ADR.5
ADR.4
ADR.3
ADR.2
ADR.1
ADR.0
ADRMK
A0h
ADR[6:0]: These 7 bits define slave address on the TWSI/IIC bus.
ADRMK: Address Mask bit. Its only compare 4 bits MSB when set this bit. When this bit
is set, ADR.2 – ADR.0 is masked to excluded from the address comparison. In
other words, it will be addressed “hit” and respond with ACK as long as ADR6-
ADR.3 is matched.
Mnemonic: TWSIC1
Address: C2h
7
6
5
4
3
2
1
0
Reset
TWSIE
-
-
-
BusBusy
TWSIFS2
TWSIFS1
TWSIFS0
01h
TWSIE: TWSI function enable bit.
BusBusy: When TWSI bus is detected with “START” condition, this bit is set. When
TWSI bus is detected with “STOP” condition, this bit is cleared. (Read only)
TWSIFS[2:0]: TWSI clock rate selector at Master mode.
TWSIFS[2:0]
SCL Frequency
000
Xtal/32
001
Xtal/64 (default)
010
Xtal/128
011
Xtal/256
100
Xtal/512
101
Xtal/1024
110
Xtal/2048
111
Xtal/4096
Mnemonic: TWSIC2
Address: C3h
7
6
5
4
3
2
1
0
Reset
MATCH
SRW
-
-
RESTART
-
-
MRW
00h
MATCH: When the first received data (following the START signal) in TWSIRXD register
is matches with the address that address register (TWSIA) set, this bit will set.
(Read only & Slave mode only)
SRW: The slave mode read (received) or wrote (transmit) on the TWSI bus. When
this bit is set, the slave module transmit data on the TWSI bus (SDA). When
this bit is clear, the slave module received data on the TWSI bus (SDA). (Read



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