BQ7693003DBT datasheet(27/63 Pages) TI1

27 / 63 page

bq76920, bq76930, bq76940

www.ti.com

SLUSBK2F – OCTOBER 2013 – REVISED NOVEMBER 2015

Table 7-1. CHG, DSG Response Under Various System Events (continued)

EVENT

[CHG_ON]

[DSG_ON]

SCD Fault

—

Set to 0

ALERT Override

Set to 0

DEVICE_XREADY is set

Set to 0

Enter SHIP mode from NORMAL

Set to 0

NOTE

All protection recovery must be initiated by the host microcontroller. In order to resume FET

operation after a fault condition has occurred, the host microcontroller must first clear the

corresponding status bit in the SYS_STAT register, which will clear the ALERT pin, and then

manually re-enable the CHG and/or DSG bit. Certain faults, such as OV or UV, may

immediately re-toggle if such a condition still persists. Refer to Table 7-3 for details on

clearing status bits.

There are no conditions under which the bq769x0 automatically sets either [CHG_ON] or [DSG_ON] to 1.

7.3.1.3.2 Load Detection

A load detection circuit is present on the CHG pin and activated whenever the CHG FET is disabled

([CHG_ON] = 0). This circuit detects if the CHG pin is externally pulled high when the high impedance

(approximately 1 M

Ω) pull-down path should actually be holding the CHG pin to VSS, and is useful for

determining if the PACK– pin (outside of the AFE) is being held at a high voltage—for example, if the load

is present while the power FETs are off. The state of the load detection circuit is read from the

[LOAD_PRESENT] bit of the SYS_CTRL1 register.

After an OCD or SCD fault has occurred, the DSG FET will be disabled ([DSG_ON] cleared), and the

CHG FET must similarly be explicitly disabled to activate the load detection circuit. The host

microcontroller may periodically poll the [LOAD_PRESENT] bit to determine the state of the PACK– pin

and determine when the load is removed ([LOAD_PRESENT] = 0).

7.3.1.3.3 Cell Balancing

Both internal and external passive cell balancing options are fully supported by the bq76920, while

external cell balancing is recommended for bq76930 and bq76940. It is left to the host controller to

determine the exact balancing algorithm to be used in any given system. Each bq769x0 device provides

the cell voltages and balancing drivers to enable this. If using the internal cell balance drivers, up to 50 mA

may be balanced per cell. If using external cell balancing, much higher balancing currents may be

employed.

To activate a particular cell balancing channel, simply set the corresponding bit for that cell in the

CELLBAL1, CELLBAL2, or CELLBAL3 register. For example, VC1–VC0 is enabled by setting [CB1], while

VC12–VC11 is set via [CB12].

Multiple cells may be simultaneously balanced. It is left to the user’s discretion to determine the ideal

number of cells to concurrently balance. Adjacent cells should not be balanced simultaneously. This may

cause cell pins to exceed their absolute maximum conditions and is also not recommended for external

balancing implementations. Additionally, if internal balancing is used, care should be taken to avoid

exceeding package power dissipation ratings.

Detailed Description

Submit Documentation Feedback

Product Folder Links: bq76920 bq76930 bq76940

BQ7693003DBT Datasheet(PDF) 27 Page - Texas Instruments

BQ7693003DBT Datasheet(HTML) 27 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL