BQ7693003DBT datasheet(28/63 Pages) TI1

28 / 63 page

bq76920, bq76930, bq76940

SLUSBK2F – OCTOBER 2013 – REVISED NOVEMBER 2015

www.ti.com

NOTE

The host controller must ensure that no two adjacent cells are balanced simultaneously

within each set of the following:

•

VC1–VC5

•

VC6–VC10

•

VC11–VC15

The total duty cycle devoted to balancing is approximately 70% per 250 ms. This is because a portion of

the 250 ms is allotted for normal cell voltage measurements via the ADC.

If [ADC_EN] =1, OV and UV protections are not affected by cell balancing, since the cell balancing is

temporarily suspended for a small slice of time every 250 ms during which the cell voltage readings are

taken. This ensures that the OV and UV protections do not accidentally trigger, or miss an actual OV/UV

condition on the cells while balancing is enabled.

NOTE

All cell balancing control bits in CELLBAL1, CELLBAL2, and CELLBAL3 are automatically

cleared under the following events, and must be explicitly re-written by the host

microcontroller following clearing of the event:

•

DEVICE_XREADY is set

•

Enters NORMAL mode from SHIP mode

7.3.1.3.4 Alert

The ALERT pin serves as an active high digital interrupt signal that can be connected to a GPIO port of

the host microcontroller. This signal is an OR of all bits in the SYS_STAT register.

In order to clear the ALERT signal, the source bit in the SYS_STAT register must first be cleared by

writing a “1” to that bit. This will cause an automatic clear of the ALERT pin once all bits are cleared.

The ALERT pin may also be driven by an external source; for example, the pack may include a secondary

overvoltage protector IC. When the ALERT pin is forced high externally while low, the device will

recognize this as an OVRD_ALERT fault and set the [OVRD_ALERT] bit. This triggers automatic disabling

of both CHG and DSG FET drivers. The device cannot recognize the ALERT signal input high when it is

already forcing the ALERT signal high from another condition.

The ALERT pin has no internal debounce support so care should be taken to protect the pin from noise or

other parasitic transients.

NOTE

It is highly recommended to place an external 500 k

Ω–1 MΩ pull-down resistor from ALERT

to VSS as close to the IC as possible. Additional recommendations are:

a) To keep all traces between the IC and components connected to the ALERT pin very

short.

b) To include a guard ring around the components connected to the ALERT pin and the

pin itself.

7.3.1.3.5 Output LDO

An adjustable output voltage regulator LDO is provided as a simple way to provide power to additional

components in the battery pack, such as the host microcontroller or LEDs. The LDO is configured in

EEPROM by TI during the production test process, and can support 2.5-V or 3.3-V options.

Detailed Description

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Product Folder Links: bq76920 bq76930 bq76940

BQ7693003DBT Datasheet(PDF) 28 Page - Texas Instruments

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