BQ7693003DBT datasheet(29/63 Pages) TI1

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...

R/W

...

C7 C6

...

Start

Slave Address

Address

Stop

SCL

SDA

...

R/W

ACK

D7 D6

ACK

NACK

Slave Address

Slave

Drives CRC

(optional)

Master

Drives NACK

Slave

Drives Data

Repeated

Start

...

R/W

...

D7 D6

...

C7 C6

...

Start

Slave Address

Address

Data

CRC

(optional)

Stop

SCL

SDA

ACK

bq76920, bq76930, bq76940

www.ti.com

SLUSBK2F – OCTOBER 2013 – REVISED NOVEMBER 2015

A cascode small-signal FET must be added in the external path between BAT and REGSRC with the

bq76930 and bq76940. This helps drop most of the power dissipation outside of the package and cuts

down on package power dissipation.

7.3.1.4

Communications Subsystem

The AFE implements a standard 100-kHz I2C interface and acts as a slave device. The I2C device

address is 7-bits and is factory programmed. Consult the Device Comparison Table (Section 4) of this

datasheet for more information.

A write transaction is shown in Figure 7-4. Block writes are allowed by sending additional data bytes

before the Stop. The I2C block will auto-increment the register address after each data byte.

When enabled, the CRC is calculated as follows:

•

In a single-byte write transaction, the CRC is calculated over the slave address, register address, and

data.

•

In a block write transaction, the CRC for the first data byte is calculated over the slave address,

The CRC polynomial is x8 + x2 + x + 1, and the initial value is 0.

When the slave detects a bad CRC, the I2C slave will NACK the CRC, which causes the I2C slave to go to

an idle state.

Figure 7-4. I2C Write

Figure 7-5 shows a read transaction using a Repeated Start.

Figure 7-5. I2C Read with Repeated Start

Figure 7-6 shows a read transaction where a Repeated Start is not used, for example if not available in

hardware. For a block read, the master ACK’s each data byte except the last and continues to clock the

interface. The I2C block will auto-increment the register address after each data byte.

When enabled, the CRC for a read transaction is calculated as follows:

•

In a single-byte read transaction, the CRC is calculated after the second start and uses the slave

address and data byte.

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BQ7693003DBT Datasheet(PDF) 29 Page - Texas Instruments

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