PI7C8150BMA-33 datasheet(34/107 Pages) PERICOM

34 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 34 of 107

April 2015 – Revision 2.1



The bus command on CBE_L is a configuration write command.

When PI7C8150B initiates the transaction on the target interface, the bus command is

changed from configuration write to special cycle. The address and data are for-warded

unchanged. Devices that use special cycles ignore the address and decode only the bus

command. The data phase contains the special cycle message. The transaction is

forwarded as a delayed transaction, but in this case the target response is not forwarded

back (because special cycles result in a master abort). Once the transaction is completed on

the target bus, through detection of the master abort condition, PI7C8150B responds with

TRDY_L to the next attempt of the con-figuration transaction from the initiator. If more

than one data transfer is requested, PI7C8150B responds with a target disconnect operation

during the first data phase.

3.8

TRANSACTION TERMINATION

This section describes how PI7C8150B returns transaction termination conditions back to

the initiator.

The initiator can terminate transactions with one of the following types of termination:



Normal termination

Normal termination occurs when the initiator de-asserts FRAME_L at the beginning of the

last data phase, and de-asserts IRDY# at the end of the last data phase in conjunction with

either TRDY_L or STOP_L assertion from the target.



Master abort

A master abort occurs when no target response is detected. When the initiator does not

detect a DEVSEL_L from the target within five clock cycles after asserting FRAME_L, the

initiator terminates the transaction with a master abort. If FRAME_L is still asserted, the

initiator de-asserts FRAME_L on the next cycle, and then de-asserts IRDY_L on the

following cycle. IRDY_L must be asserted in the same cycle in which FRAME_L de-

asserts. If FRAME_L is already de-asserted, IRDY_L can be de-asserted on the next clock

cycle following detection of the master abort condition.

The target can terminate transactions with one of the following types of termination:



Normal termination

TRDY_L and DEVSEL_L asserted in conjunction with FRAME_L de-asserted and

IRDY_L asserted.



Target retry

STOP_L and DEVSEL_L asserted with TRDY_L de-asserted during the first data phase.

No data transfers occur during the transaction. This transaction must be repeated.



Target disconnect with data transfer

STOP_L, DEVSEL_L and TRDY_L asserted. It signals that this is the last data transfer of

the transaction.



Target disconnect without data transfer

STOP_L and DEVSEL_L asserted with TRDY_L de-asserted after previous data transfers

have been made. Indicates that no more data transfers will be made during this transaction.



Target abort

15-0048

PI7C8150BMA-33 Datasheet(PDF) 34 Page - Pericom Semiconductor Corporation

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