PI7C8150BMA-33 datasheet(98/107 Pages) PERICOM

98 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 98 of 107

April 2015 – Revision 2.1

16.3

TAP TEST DATA REGISTERS

The PI7C8150B contains two test data registers (bypass and boundary-scan). Each test

data register selected by the TAP controller is connected serially between TDI and TDO.

TDI is connected to the test data register’s most significant bit. TDO is connected to the

least significant bit. Data is shifted one bit position within the register towards TDO on

each rising edge of TCK. While any register is selected, data is transferred from TDI to

TDO without inversion. The following sections describe each of the test data registers.

16.4

BYPASS REGISTER

The required bypass register, a one-bit shift register, provides the shortest path between

TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test

data to and from other components on the board. This path can be selected when no test

operation is being performed on the PI7C8150B.

16.5

BOUNDARY-SCAN REGISTER

The boundary-scan register contains a cell for each pin as well as control cells for I/O and

the high-impedance pin.

Table Table 16-1 shows the bit order of the PI7C8150B boundary-scan register. All table

cells that contain “Control” select the direction of bi-directional pins or high-impedance

output pins. When a “1” is loaded into the control cell, the associated pin(s) are high-

impedance or selected as output.

The boundary-scan register is a required set of serial-shiftable register cells, configured in

master/slave stages and connected between each of the PI7C8150B’s pins and on-chip

system logic. The VDD, GND, and JTAG pins are NOT in the boundary-scan chain.

The boundary-scan register cells are dedicated logic and do not have any system function.

Data may be loaded into the boundary-scan register master cells from

the device input pins and output pin-drivers in parallel by the mandatory SAMPLE and

EXTEST instructions. Parallel loading takes place on the rising edge of TCK.

Data may be scanned into the boundary-scan register serially via the TDI serial input pin,

clocked by the rising edge of TCK. When the required data has been loaded into the

master-cell stages, it can be driven into the system logic at input pins or onto the output

pins on the falling edge of TCK state. Data may also be shifted out of the boundary-scan

16.6

TAP CONTROLLER

The TAP (Test Access Port) controller is a 4-state synchronous finite state machine that

controls the sequence of test logic operations. The TAP can be controlled via a bus master.

The bus master can be either automatic test equipment or a component (i.e., PLD) that

interfaces to the TAP. The TAP controller changes state only in response to a rising edge of

TCK. The value of the test mode state (TMS) input signal at a rising edge of TCK controls

the sequence of state changes. The TAP controller is initialized after power-up by applying

15-0048

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