PI7C8150BMA-33 datasheet(31/107 Pages) PERICOM

31 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 31 of 107

April 2015 – Revision 2.1

3.7.1

TYPE 0 ACCESS TO PI7C8150B

The configuration space is accessed by a Type 0 configuration transaction on the primary

interface. The configuration space cannot be accessed from the secondary bus. The

PI7C8150B responds to a Type 0 configuration transaction by asserting P_DEVSEL_L

when the following conditions are met during the address phase:



The bus command is a configuration read or configuration write transaction.



Lowest two address bits P_AD[1:0] must be 00b.



Signal P_IDSEL must be asserted.

PI7C8150B limits all configuration access to a single DWORD data transfer and returns

target-disconnect with the first data transfer if additional data phases are requested.

Because read transactions to configuration space do not have side effects, all bytes in the

requested DWORD are returned, regardless of the value of the byte enable bits.

Type 0 configuration write and read transactions do not use data buffers; that is, these

transactions are completed immediately, regardless of the state of the data buffers. The

PI7C8150B ignores all Type 0 transactions initiated on the secondary interface.

3.7.2

TYPE 1 TO TYPE 0 CONVERSION

Type 1 configuration transactions are used specifically for device configuration in a

hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should

respond to a Type 1 configuration command. Type 1 configuration commands are used

when the configuration access is intended for a PCI device that resides on a PCI bus other

than the one where the Type 1 transaction is generated.

PI7C8150B performs a Type 1 to Type 0 translation when the Type 1 transaction is

generated on the primary bus and is intended for a device attached directly to the secondary

bus. PI7C8150B must convert the configuration command to a Type 0 format so that the

secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in

the downstream direction; that is, PI7C8150B generates a Type 0 transaction only on the

secondary bus, and never on the primary bus.

PI7C8150B responds to a Type 1 configuration transaction and translates it into a Type 0

transaction on the secondary bus when the following conditions are met during the address

phase:



The lowest two address bits on P_AD[1:0] are 01b.



The bus number in address field P_AD[23:16] is equal to the value in the secondary

bus number register in configuration space.



The bus command on P_CBE[3:0] is a configuration read or configuration write

transaction.

When PI7C8150B translates the Type 1 transaction to a Type 0 transaction on the

secondary interface, it performs the following translations to the address:



Sets the lowest two address bits on S_AD[1:0].

15-0048

PI7C8150BMA-33 Datasheet(PDF) 31 Page - Pericom Semiconductor Corporation

PI7C8150BMA-33 Datasheet(HTML) 31 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL