PI7C8150BMA-33 datasheet(28/107 Pages) PERICOM

28 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 28 of 107

April 2015 – Revision 2.1

transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is

discarded.

Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB

address boundary, or until the initiator de-asserts FRAME_L. Section 3.6.6 describes flow-

through mode during read operations.

Table 3-4 shows the read pre-fetch address boundaries for read transactions during non-

flow-through mode.

Table 3-4. Read Prefetch Address Boundaries

Type of Transaction

Address Space

Cache

Line

Size

(CLS)

Prefetch

Aligned

Address

Boundary

Configuration Read

One DWORD (no prefetch)

I/O Read

One DWORD (no prefetch)

Memory Read

Non-Prefetchable

One DWORD (no prefetch)

Memory Read

Prefetchable

CLS = 0 or 16

16-DWORD aligned address

boundary

Memory Read

Prefetchable

CLS = 1, 2, 4, 8, 16

Cache line address boundary

Memory Read Line

CLS = 0 or 16

16-DWORD aligned address

boundary

Memory Read Line

CLS = 1, 2, 4, 8, 16

Cache line boundary

Memory Read Multiple

CLS = 0 or 16

32-DWORD aligned address

boundary

Memory Read Multiple

CLS = 1, 2, 4, 8, 16

2X of cache line boundary

- does not matter if it is prefetchable or non-prefetchable

* don’t care

Table 3-5. Read Transaction Prefetching

Type of Transaction

Read Behavior

I/O Read

Prefetching never allowed

Configuration Read

Prefetching never allowed

Memory Read

Downstream: Prefetching used if address is prefetchable space

Upstream: Prefetching used or programmable

Memory Read Line

Prefetching always used

Memory Read Multiple

Prefetching always used

See Section 4.3 for detailed information about prefetchable and non-prefetchable address spaces.

3.6.4

DELAYED READ REQUESTS

PI7C8150B treats all read transactions as delayed read transactions, which means

that the read request from the initiator is posted into a delayed transaction queue.

Read data from the target is placed in the read data queue directed toward the initiator bus

interface and is transferred to the initiator when the initiator repeats

the read transaction.

When PI7C8150B accepts a delayed read request, it first samples the read address, read bus

command, and address parity. When IRDY_L is asserted, PI7C8150B then samples the

byte enable bits for the first data phase. This information is entered into the delayed

transaction queue. PI7C8150B terminates the transaction by signaling a target retry to the

initiator. Upon reception of the target retry, the initiator is required to continue to repeat the

same read transaction until at least one data transfer is completed, or until a target response

(target abort or master abort) other than a target retry is received.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 28 Page - Pericom Semiconductor Corporation

PI7C8150BMA-33 Datasheet(HTML) 28 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL