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PI7C8150BMA-33 Datasheet(PDF) 88 Page - Pericom Semiconductor Corporation |
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PI7C8150BMA-33 Datasheet(HTML) 88 Page - Pericom Semiconductor Corporation |
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88 / 107 page  PI7C8150B ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE Page 88 of 107 April 2015 – Revision 2.1 Bit Function Type Description 7:6 Clock 3 disable R/W If either bit is 0, then S_CLKOUT [3] is enabled. If both bits are 1, then S_CLKOUT [3] is disabled. 8 Clock 4 disable R/W If bit is 0, then S_CLKOUT [4] is enabled. If bit is 1, then S_CLKOUT [4] is disabled and driven low. 9 Clock 5 disable R/W If bit is 0, then S_CLKOUT [5] is enabled. If bit is 1, then S_CLKOUT [5] is disabled and driven low. 10 Clock 6 disable R/W If bit is 0, then S_CLKOUT [6] is enabled. If bit is 1, then S_CLKOUT [6] is disabled and driven low. 11 Clock 7 disable R/W If bit is 0, then S_CLKOUT [7] is enabled. If bit is 1, then S_CLKOUT [7] is disabled and driven low. 12 Clock 8 disable R/W If bit is 0, then S_CLKOUT [8] is enabled. If bit is 1, then S_CLKOUT [8] is disabled and driven low. 13 Clock 9 disable R/W If bit is 0, then S_CLKOUT [9] is enabled. If bit is 1, then S_CLKOUT [9] is disabled and driven low. 15:14 Reserved RO Reserved. Returns 00 when read. 14.1.41 P_SERR_L STATUS REGISTER – OFFSET 68h Bit Function Type Description 16 Address Parity Error R/WC 1: Signal P_SERR_L was asserted because an address parity error was detected on P or S bus. Reset to 0 17 Posted Write Data Parity Error R/WC 1: Signal P_SERR_L was asserted because a posted write data parity error was detected on the target bus. Reset to 0 18 Posted Write Non-delivery R/WC 1: Signal P_SERR_L was asserted because the bridge was unable to deliver post memory write data to the target after 2 24 attempts. Reset to 0 19 Target Abort during Posted Write R/WC 1: Signal P_SERR_L was asserted because the bridge received a target abort when delivering post memory write data. Reset to 0. 20 Master Abort during Posted Write R/WC 1: Signal P_SERR_L was asserted because the bridge received a master abort when attempting to deliver post memory write data Reset to 0. 21 Delayed Write Non-delivery R/WC 1: Signal P_SERR_L was asserted because the bridge was unable to deliver delayed write data after 2 24 attempts. Reset to 0 22 Delayed Read – No Data from Target R/WC 1: Signal P_SERR_L was asserted because the bridge was unable to read any data from the target after 2 24 attempts. Reset to 0. 23 Delayed Transaction Master Timeout R/WC 1: Signal P_SERR_L was asserted because a master did not repeat a read or write transaction before master timeout. Reset to 0. 14.1.42 PORT OPTION REGISTER – OFFSET 74h Bit Function Type Description 0 Reserved R/O Reserved. Returns 0 when read. 15-0048 |
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