PI7C8150BMA-33 datasheet(30/107 Pages) PERICOM

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PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 30 of 107

April 2015 – Revision 2.1

pending data for other transactions in the RDB (Read Data Buffer), the remaining read data

will be discarded even though the master timeout timer has not expired.

PI7C8150B implements a master timeout timer that starts counting when the delayed read

completion is at the head of the delayed transaction queue, and the read data is at the head

of the read data queue. The initial value of this timer is programmable through

configuration register. If the initiator does not repeat the read transaction and before the

master timeout timer expires (2

15 default), PI7C8150B discards the read transaction and

read data from its queues. PI7C8150B also conditionally asserts P_SERR_L (see Section

6.4).

PI7C8150B has the capability to post multiple delayed read requests, up to a maximum of

four in each direction. If an initiator starts a read transaction that matches the address and

read command of a read transaction that is already queued, the current read command is not

posted as it is already contained in the delayed transaction queue.

See Section 5 for a discussion of how delayed read transactions are ordered when crossing

PI7C8150B.

3.6.7

FAST BACK-TO-BACK READ TRANSACTION

PI7C8150B can recognize fast back-to-back read transactions.

3.7

CONFIGURATION TRANSACTIONS

Configuration transactions are used to initialize a PCI system. Every PCI device has a

configuration space that is accessed by configuration commands. All registers are

accessible in configuration space only.

In addition to accepting configuration transactions for initialization of its own

configuration space, the PI7C8150B also forwards configuration transactions for device

initialization in hierarchical PCI systems, as well as for special cycle generation.

To support hierarchical PCI bus systems, two types of configuration transactions are

specified: Type 0 and Type 1.

Type 0 configuration transactions are issued when the intended target resides on the same

PCI bus as the initiator. A Type 0 configuration transaction is identified by the

configuration command and the lowest two bits of the address set to 00b.

Type 1 configuration transactions are issued when the intended target resides on another

PCI bus, or when a special cycle is to be generated on another PCI bus. A Type 1

configuration command is identified by the configuration command and the lowest two

address bits set to 01b.

The register number is found in both Type 0 and Type 1 formats and gives the DWORD

address of the configuration register to be accessed. The function number is also included

in both Type 0 and Type 1 formats and indicates which function of a multifunction device

is to be accessed. For single-function devices, this value is not decoded. The addresses of

Type 1 configuration transaction include a 5-bit field designating the device number that

identifies the device on the target PCI bus that is to be accessed. In addition, the bus

number in Type 1 transactions specifies the PCI bus to which the transaction is targeted.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 30 Page - Pericom Semiconductor Corporation

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