PI7C8150BMA-33 datasheet(15/107 Pages) PERICOM

15 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 15 of 107

April 2015 – Revision 2.1

Name

Pin #

Type

Description

S_DEVSEL_L

175

A11

STS

Secondary Device Select (Active LOW): Asserted by

the target indicating that the device is accepting the

transaction. As a master, PI7C8150B waits for the

assertion of this signal within 5 cycles of S_FRAME_L

assertion; otherwise, terminate with master abort. Before

tri-stated, it is driven to a de-asserted state for one cycle.

S_STOP_L

173

B11

STS

Secondary STOP (Active LOW): Asserted by the

target indicating that the target is requesting the initiator

to stop the current transaction. Before tri-stated, it is

driven to a de-asserted state for one cycle.

S_LOCK_L

172

C11

STS

Secondary LOCK (Active LOW): Asserted by the

master for multiple transactions to complete.

S_PERR_L

171

A12

STS

Secondary Parity Error (Active LOW): Asserted

when a data parity error is detected for data received on

the secondary interface. Before being tri-stated, it is

driven to a de-asserted state for one cycle.

S_SERR_L

169

D11

Secondary System Error (Active LOW): Can be

driven LOW by any device to indicate a system error

condition.

S_REQ_L[8:0]

9, 8, 7, 6, 5, 4, 3,

2, 207

E4, E3, D2, C1,

C2, D3, A2,B3,

Secondary Request (Active LOW): This is asserted by

an external device to indicate that it wants to start a

transaction on the secondary bus. The input is externally

pulled up through a resistor to VDD.

S_GNT_L[8:0]

19, 18, 17, 16, 15,

14, 13, 11, 10

G1, F1, F2, G3,

F4, E1, E2,F3,

Secondary Grant (Active LOW): PI7C8150B asserts

this pin to access the secondary bus. PI7C8150B de-

asserts this pin for at least 2 PCI clock cycles before

asserting it again. During idle and S_GNT_L asserted,

PI7C8150B will drive S_AD, S_CBE, and S_PAR.

S_RESET_L

Secondary RESET (Active LOW): Asserted when any

of the following conditions are met:

Signal P_RESET_L is asserted.

Secondary reset bit in bridge control register in

configuration space is set.

When asserted, all control signals are tri-stated and

zeroes are driven on S_AD, S_CBE, and S_PAR.

S_M66EN

153

D15

I/OD

Secondary Interface 66MHz Operation:

In synchronous mode, this input is used to specify if

PI7C8150B is running at 66MHz on the secondary side.

When HIGH, the Secondary bus may run at 66MHz.

When LOW, the Secondary bus may only run at

33MHz.

If P_M66EN is pulled LOW, the S_M66EN is also

driven LOW.

In asynchronous mode, S_M66EN is an input pin and

operates independently from P_M66EN. S_M66EN

should be pulled up to a logic “1” when the secondary

frequency is 66MHz, or pulled down to a logic “0” when

the secondary frequency is 33MHz.

S_CFN_L

Secondary Bus Central Function Control Pin: When

tied LOW, it enables the internal arbiter. When tied

HIGH, an external arbiter must be used. S_REQ_L[0] is

reconfigured to be the secondary bus grant input, and

S_GNT_L[0] is reconfigured to be the secondary bus

request output. S_CFN_L has a weak internal pull-

down resistor.

2.2.3

CLOCK SIGNALS

Name

Pin #

Type

Description

P_CLK

Primary Clock Input: Provides timing for all

transactions on the primary interface.

S_CLKIN

Secondary Clock Input: Provides timing for all

transactions on the secondary interface.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 15 Page - Pericom Semiconductor Corporation

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