PI7C8150BMA-33 datasheet(68/107 Pages) PERICOM

68 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 68 of 107

April 2015 – Revision 2.1



Write-1-to-clear signal output enable control field



Input data field

The bottom four bits of the output enable fields control whether each GPIO signal is input

only or bi-directional. Each signal is controlled independently by a bit in each output

enable control field. If a 1 is written to the write-1-to-set field, the corresponding pin is

activated as an output. If a 1 is written to the write-1-to-clear field, the output driver is tri-

stated, and the pin is then input only. Writing zeroes to these registers has no effect. The

reset for these signals is input only.

The input data field is read only and reflects the current value of the GPIO pins. A type 0

configuration read operation to this address is used to obtain the values of these pins. All

pins can be read at any time, whether configured as input only or as bi-directional.

The output data fields also use the write-1-to-set and write-1-to-clear mode. If a 1 is

written to the write-1-to-set field and the pin is enabled as an output, the corresponding

GPIO output is driven HIGH. If a 1 is written to the write-1-to-clear field and the pin is

enabled as an output, the corresponding GPIO output is driven LOW. Writing zeros to

these registers has no effect. The value written to the output register will be driven only

when the GPIO signal is configured as bi-directional. A type 0 configuration write

operation is used to program these fields. The rest value for the output is 0.

10.2

SECONDARY CLOCK CONTROL

The PI7C8150B uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data

stream. This data stream is shifted into the secondary clock control register and is used for

selectively disabling secondary clock outputs.

The serial data stream is shifted in as soon as P_RST_L is detected deasserted and the

secondary reset signal, S_RST_L, is detected asserted. The deassertion of S_RST_L is

delayed until the PI7C8150B completes shifting in the clock mask data, which takes 23

clock cycles. After that, the GPIO pins can be used as general-purpose I/O pins.

An external shift register should be used to load and shift the data. The GPIO pins are used

for shift register control and serial data input. Table 10-1 shows the operation of the GPIO

pins.

Table 10-1. GPIO Operation

GPIO Pin

Operation

GPIO[0]

Shift register clock output at 33MHz max frequency

GPIO[1]

Not used

GPIO[2]

Shift register control

0: Load

1: Shift

GPIO[3]

Not used

The data is input through the dedicated input signal, MSK_IN.

The shift register circuitry is not necessary for correct operation of PI7C8150B. The shift

outputs or tied HIGH to force all secondary clock outputs HIGH. Table 10-2 shows the

format of the serial stream.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 68 Page - Pericom Semiconductor Corporation

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