PI7C8150BMA-33 datasheet(91/107 Pages) PERICOM

91 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 91 of 107

April 2015 – Revision 2.1

14.1.45

PRIMARY BUS MASTER TIMEOUT COUNTER – OFFSET 80h

Bit

Function

Type

Description

31:16

Primary Timeout

R/W

There are 2 control settings for the primary bus master timeout

counter. Bit[24] offset 3Ch can set the counter to either 2

10 or 215

clocks. Bit[31:16] offset 80h may control the granularity down to 1

PCI clock (from 0h to FFFFh). Both controls will over-write each

other, with the last write value being used for the initial value loaded

into the timeout counter. The timeout counter will start after the last

data (if less than a cache line) or the first cache line data (if more than

one cache line) is completed to the bridge. Once the timeout counter

expires, the corresponding data in the buffer will be discarded.

Reset to 8000h.

14.1.46

CAPABILITY ID REGISTER – OFFSET B0h

Bit

Function

Type

Description

7:0

Capability ID

R/O

Capability ID for slot identification

00h: Reserved

01h: PCI Power Management (PCIPM)

02h: Accelerated Graphics Port (AGP)

03h: Vital Product Data (VPD)

04h: Slot Identification (SI)

05h: Message Signaled Interrupts (MSI)

06h: Compact PCI Hot Swap (CHS)

07h – 255h: Reserved

Reset to 04h

14.1.47

NEXT POINTER REGISTER – OFFSET B0h

Bit

Function

Type

Description

15:8

Next Pointer

R/O

Next pointer =11100100: next pointer(E4h if HS_EN=1)

=00000000: next pointer(00h if HS_EN=0)

14.1.48

SLOT NUMBER REGISTER – OFFSET B0h

Bit

Function

Type

Description

20:16

Expansion Slot

Number

R/W

Determines expansion slot number

Reset to 0

First in Chassis

R/W

First in chassis

Reset to 0

23:22

Reserved

R/O

Reserved. Returns 0 when read.

14.1.49

CHASSIS NUMBER REGISTER – OFFSET B0h

Bit

Function

Type

Description

31:24

Chassis Number

R/W

Chassis number register.

Reset to 0

15-0048

PI7C8150BMA-33 Datasheet(PDF) 91 Page - Pericom Semiconductor Corporation

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