PI7C8150BMA-33 datasheet(89/107 Pages) PERICOM

89 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 89 of 107

April 2015 – Revision 2.1

Bit

Function

Type

Description

Primary MEMR

Command Alias

Enable

R/W

Controls PI7C8150B’s detection mechanism for matching memory

read retry cycles from the initiator on the primary interface

0: exact matching for non-posted memory write retry cycles from

initiator on the primary interface

1: alias MEMRL or MEMRM to MEMR for memory read retry

cycles from the initiator on the primary interface

Reset to 1

Primary MEMW

Command Alias

Enable

R/W

Controls PI7C8150B’s detection mechanism for matching non-posted

memory write retry cycles from the initiator on the primary interface

0: exact matching for non-posted memory write retry cycles from

initiator on the primary interface

1: alias MEMWI to MEMW for non-posted memory write retry

cycles from initiator on the primary interface

Reset to 0

Secondary

MEMR

Command Alias

Enable

R/W

Controls PI7C8150B’s detection mechanism for matching memory

read retry cycles from the initiator on the secondary

0: exact matching for memory read retry cycles from initiator on the

secondary interface

1: alias MEMRL or MEMRM to MEMR for memory read retry

cycles from initiator on the secondary interface

Reset to 1

Secondary

MEMW

Command Alias

Enable

R/W

Controls PI7C8150B’s detection mechanism for matching non-posted

memory write retry cycles from the initiator on the primary interface

0: exact matching for non-posted memory write retry cycles from

initiator on the secondary interface

1: alias MEMWI to MEMW for non-posted memory write retry

cycles from initiator on the secondary interface

Reset to 0

Primary MEMR

Line/Multiple

Alias Enable

R/W

0: exact matching for memory read line/multiple retry cycle from

initiator on primary interface

1: alias MEMRL to MEMRM or MEMRM to MEMRL for memory

read retry cycle from initiator on primary interface

Reset to 1

Secondary

MEMR

Line/Multiple

Alias Enable

R/W

0: exact matching for memory read line/multiple retry cycle from

initiator on secondary interface

1: alias MEMRL to MEMRM or MEMRM to MEMRL for memory

read retry cycle from initiator on secondary interface

Reset to 1

Primary

MEMWI

Command Alias

Enable

R/W

Controls PI7C8150B’s detection mechanism for matching non-posted

memory write and invalidate cycles from the initiator on the primary

interface

0: When accepting MEMWI command at the primary interface,

PI7C8150B converts MEMWI to MEMW command on the

secondary interface

1: Disconnects MEMWI command at aligned cache line boundaries

Reset to 0

15-0048

PI7C8150BMA-33 Datasheet(PDF) 89 Page - Pericom Semiconductor Corporation

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