PI7C8150BMA-33 datasheet(79/107 Pages) PERICOM

79 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 79 of 107

April 2015 – Revision 2.1

Bit

Function

Type

Description

Master Data

Parity Error

Detected

R/WC

Set to 1 when S_PERR_L is asserted and bit 6 of command register

is set

Reset to 0

26:25

DEVSEL_L

timing

R/O

DEVSEL# timing (medium decoding)

00: fast DEVSEL_L decoding

01: medium DEVSEL_L decoding

10: slow DEVSEL_L decoding

11: reserved

Reset to 01

Signaled Target

Abort

R/WC

Set to 1 (by a target device) whenever a target abort cycle occurs on

its secondary interface

Reset to 0

Received Target

Abort

R/WC

Set to 1 (by a master device) whenever transactions on its secondary

interface are terminated with target abort

Reset to 0

Received Master

Abort

R/WC

Set to 1 (by a master) when transactions on its secondary interface

are terminated with Master Abort

Reset to 0

Received System

Error

R/WC

Set to 1 when S_SERR_L is asserted

Reset to 0

Detected Parity

Error

R/WC

Set to 1 when address or data parity error is detected on the

secondary interface

Reset to 0

14.1.17

MEMORY BASE REGISTER – OFFSET 20h

Bit

Function

Type

Description

3:0

R/O

Lower four bits of register are read only and return 0.

Reset to 0

15:4

Memory Base

Address [15:4]

R/W

Defines the bottom address of an address range for the bridge to

determine when to forward memory transactions from one interface

to the other. The upper 12 bits correspond to address bits [31:20]

and are writable. The lower 20 bits corresponding to address bits

[19:0] are assumed to be 0.

Reset to 0

14.1.18

MEMORY LIMIT REGISTER – OFFSET 20h

Bit

Function

Type

Description

19:16

R/O

Lower four bits of register are read only and return 0.

Reset to 0

31:20

Memory Limit

Address [31:20]

R/W

Defines the top address of an address range for the bridge to

determine when to forward memory transactions from one interface

to the other. The upper 12 bits correspond to address bits [31:20]

and are writable. The lower 20 bits corresponding to address bits

[19:0] are assumed to be FFFFFh.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 79 Page - Pericom Semiconductor Corporation

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