PI7C8150BMA-33 datasheet(63/107 Pages) PERICOM

63 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 63 of 107

April 2015 – Revision 2.1

When the last locked transaction is a posted write transaction, PI7C8150B de-asserts

LOCK_L on the target bus at the end of the transaction because the lock was relinquished

at the end of the write transaction on the initiator bus.

When PI7C8150B receives a target abort or a master abort in response to a locked delayed

transaction, PI7C8150B returns a target abort or a master abort when the initiator repeats

the locked transaction. The initiator must then de-assert LOCK_L at the end of the

transaction. PI7C8150B sets the appropriate status bits, flagging the abnormal target

termination condition (see Section 3.8). Normal forwarding of unlocked posted and

delayed transactions is resumed.

When PI7C8150B receives a target abort or a master abort in response to a locked posted

write transaction, PI7C8150B cannot pass back that status to the initiator. PI7C8150B

asserts SERR_L on the initiator bus when a target abort or a master abort is received during

a locked posted write transaction, if the SERR_L enable bit is set in the command register.

Signal SERR_L is asserted for the master abort condition if the master abort mode bit is set

in the bridge control register (see Section 6.4).

PCI BUS ARBITRATION

PI7C8150B must arbitrate for use of the primary bus when forwarding upstream

transactions. Also, it must arbitrate for use of the secondary bus when forwarding

downstream transactions. The arbiter for the primary bus resides external to PI7C8150B,

typically on the motherboard. For the secondary PCI bus, PI7C8150B implements an

internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead.

This chapter describes primary and secondary bus arbitration.

8.1

PRIMARY PCI BUS ARBITRATION

PI7C8150B implements a request output pin, P_REQ_L, and a grant input pin, P_GNT_L,

for primary PCI bus arbitration. PI7C8150B asserts P_REQ_L when forwarding

transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least

one pending transaction resides in the queues in the upstream direction, either posted write

data or delayed transaction requests, PI7C8150B keeps P_REQ_L asserted. However, if a

target retry, target disconnect, or a target abort is received in response to a transaction

initiated by PI7C8150B on the primary PCI bus, PI7C8150B de-asserts P_REQ_L for two

PCI clock cycles.

For all cycles through the bridge, P_REQ_L is not asserted until the transaction request has

been completely queued. When P_GNT_L is asserted LOW by the primary bus arbiter

after PI7C8150B has asserted P_REQ_L, PI7C8150B initiates a transaction on the primary

bus during the next PCI clock cycle. When P_GNT_L is asserted to PI7C8150B when

P_REQ_L is not asserted, PI7C8150B parks P_AD, P_CBE, and P_PAR by driving them

to valid logic levels. When the primary bus is parked at PI7C8150B and PI7C8150B has a

transaction to initiate on the primary bus, PI7C8150B starts the transaction if P_GNT_L

was asserted during the previous cycle.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 63 Page - Pericom Semiconductor Corporation

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