PI7C8150BMA-33 datasheet(62/107 Pages) PERICOM

62 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 62 of 107

April 2015 – Revision 2.1

Once the intended target has been locked, any subsequent locked transactions initiated on

the initiator bus that are forwarded by PI7C8150B are driven as locked transactions on the

target bus.

The first transaction to establish LOCK_L must be Memory Read. If the first transaction is

not Memory read, the following transactions behave accordingly:



Type 0 Configuration Read/Write induces master abort



Type 1 Configuration Read/Write induces master abort



I/O Read induces master abort



I/O Write induces master abort



Memory Write induces master abort

When PI7C8150B receives a target abort or a master abort in response to the delayed

locked read transaction, this status is passed back to the initiator, and no locks are

established on either the target or the initiator bus. PI7C8150B resumes forwarding

unlocked transactions in both directions.

7.2.2

LOCKED TRANSACTION IN UPSTREAM DIRECTION

PI7C8150B ignores upstream lock and transactions. PI7C8150B will pass these

transactions as normal transactions without lock established.

7.3

ENDING EXCLUSIVE ACCESS

After the lock has been acquired on both initiator and target buses, PI7C8150B must

maintain the lock on the target bus for any subsequent locked transactions until the initiator

relinquishes the lock.

The only time a target-retry causes the lock to be relinquished is on the first transaction of a

locked sequence. On subsequent transactions in the sequence,

the target retry has no effect on the status of the lock signal.

An established target lock is maintained until the initiator relinquishes the lock.

PI7C8150B does not know whether the current transaction is the last one in a sequence of

locked transactions until the initiator de-asserts the LOCK_L signal at end of the

transaction.

When the last locked transaction is a delayed transaction, PI7C8150B has already

completed the transaction on the target bus. In this example, as soon as PI7C8150B detects

that the initiator has relinquished the LOCK_L signal by sampling it in the de-asserted state

while FRAME_L is de-asserted, PI7C8150B de-asserts the LOCK_L signal on the target

bus as soon as possible. Because of this behavior, LOCK_L may not be de-asserted until

several cycles after the last locked transaction has been completed on the target bus. As

soon as PI7C8150B has de-asserted LOCK_L to indicate the end of a sequence of locked

transactions, it resumes forwarding unlocked transactions.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 62 Page - Pericom Semiconductor Corporation

PI7C8150BMA-33 Datasheet(HTML) 62 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL