PI7C8150BMA-33 datasheet(90/107 Pages) PERICOM

90 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 90 of 107

April 2015 – Revision 2.1

Bit

Function

Type

Description

Secondary

MEMWI

Command Alias

Enable

R/W

Controls PI7C8150B’s detection mechanism for matching non-posted

memory write and invalidate cycles from the initiator on the

secondary interface

0: When accepting MEMWI command at the secondary interface,

PI7C8150B converts MEMWI to MEMW command on the primary

interface

1: Disconnects MEMWI command at aligned cache line boundaries

Reset to 0

Enable Long

Request

R/W

Controls PI7C8150B’s ability to enable long requests for lock cycles

0: normal lock operation

1: enable long request for lock cycle

Reset to 0

Enable

Secondary To

Hold Request

Longer

R/W

Control’s PI7C8150B’s ability to enable the secondary bus to hold

requests longer.

0: internal secondary master will release REQ_L after FRAME_L

assertion

1: internal secondary master will hold REQ_L until there is no

transactions pending in FIFO or until terminated by target

Reset to 1

Enable Primary

To Hold Request

Longer

R/W

Control’s PI7C8150B’s ability to hold requests longer at the Primary

Port.

0: internal Primary master will release REQ_L after FRAME_L

assertion

1: internal Primary master will hold REQ_L until there is no

transactions pending in FIFO or until terminated by target

Reset to 1

15:12

Reserved

R/O

Reserved. Returns 0 when read.

14.1.43

RETRY COUNTER REGISTER – OFFSET 78h

Bit

Function

Type

Description

31:0

Retry Counter

R/W

Holds the maximum number of attempts that PI7C8150B will try

before reporting retry timeout. Retry count set at 2

24 PCI clocks.

Default is 0100 0000h.

14.1.44

SECONDARY BUS MASTER TIMEOUT COUNTER – OFFSET 80h

Bit

Function

Type

Description

15:0

Secondary

Timeout

R/W

There are 2 control settings for the secondary bus master timeout

counter. Bit[25] offset 3Ch can set the counter to either 2

10 or 215

clocks. Bit[15:0] offset 80h may control the granularity down to 1

PCI clock (from 0h to FFFFh). Both controls will over-write each

other, with the last write value being used for the initial value loaded

into the timeout counter. The timeout counter will start after the last

data (if less than a cache line) or the first cache line data (if more than

one cache line) is completed to the bridge. Once the timeout counter

expires, the corresponding data in the buffer will be discarded.

Reset to 8000h.

15-0048

PI7C8150BMA-33 Datasheet(PDF) 90 Page - Pericom Semiconductor Corporation

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