PI7C8150BMA-33 datasheet(73/107 Pages) PERICOM

73 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 73 of 107

April 2015 – Revision 2.1

P_CBE [3:0]

Command

Action

bridge (but not equal to the secondary bus): claim and pass

through unchanged as a Type 1 Configuration Write.

3. Otherwise, ignore.

Configuration Write as Special Cycle Request

(device = 1Fh, function = 7h)

1. If the target bus is the bridges secondary bus:

claim and pass through as a special cycle.

2. If the target bus is a subordinate bus that exists

behind the bridge (but not equal to the secondary

bus): claim and pass through unchanged as a type

1 Configuration Write.

3. Otherwise ignore

1100

Memory Read

Multiple

Same as Memory Read

1101

Dual Address Cycle

Supported

1110

Memory Read Line

Same as Memory Read

1111

Memory Write and

Invalidate

Same as Memory Read

13.2

SECONDARY INTERFACE

S_CBE[3:0]

Command

Action

0000

Interrupt

Acknowledge

Ignore

0001

Special Cycle

Do not claim. Ignore.

0010

I/O Read

Same as Primary Interface

0011

I/O Write

Same as I/O Read.

0100

Reserved

-----

0101

Reserved

-----

0110

Memory Read

Same as Primary Interface

0111

Memory Write

Same as Memory Read.

1000

Reserved

-----

1001

Reserved

-----

1010

Configuration Read

Ignore

1011

Configuration Write

I. Type 0 Configuration Write: Ignore

II. Type 1 Configuration Write (not special cycle

request):Ignore

III. Configuration Write as Special Cycle Request (device

= 1Fh, function = 7h):

1. If the target bus is the bridge’s primary bus: claim and

pass through as a Special Cycle

2. If the target bus is neither the primary bus nor is it in range

of buses defined by the bridge’s secondary and subordinate

bus registers: claim and pass through unchanged as a Type 1

Configuration Write.

3. If the target bus is not the bridge’s primary bus, but is in

range of buses defined by the bridge’s secondary and

subordinate bus registers: ignore.

1100

Memory Read

Multiple

Same as Memory Read

1101

Dual Address Cycle

Supported

1110

Memory Read Line

Same as Memory Read

1111

Memory Write and

Invalidate

Same as Memory Read

15-0048

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