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DAC8750IPWPR Datasheet(PDF) 17 Page - Texas Instruments |
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DAC8750IPWPR Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 53 page  -0.12 -0.09 -0.06 -0.03 0.00 0.03 0.06 0.09 0.12 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) 0 mA to 20 mA Internal RSET 0 mA to 24 mA Internal RSET 4 mA to 20 mA Internal RSET 0 mA to 20 mA External RSET 0 mA to 24 mA External RSET 4 mA to 20 mA External RSET C007 36 37 38 39 40 41 42 43 44 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) C001 -0.18 -0.12 -0.06 0.00 0.06 0.12 0.18 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) 0 mA to 20 mA Internal RSET 0 mA to 24 mA Internal RSET 4 mA to 20 mA Internal RSET 0 mA to 20 mA External RSET 0 mA to 24 mA External RSET 4 mA to 20 mA External RSET C006 -0.12 -0.09 -0.06 -0.03 0.00 0.03 0.06 0.09 0.12 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (oC) 0 mA to 20 mA Internal RSET 0 mA to 24 mA Internal RSET 4 mA to 20 mA Internal RSET 0 mA to 20 mA External RSET 0 mA to 24 mA External RSET 4 mA to 20 mA External RSET C003 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 10 14 18 22 26 30 34 38 AVDD (V) C008 Max DNL Min DNL -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 10 14 18 22 26 30 34 38 AVDD (V) C007 Max DNL Min DNL 17 DAC7750, DAC8750 www.ti.com SBAS538B – DECEMBER 2013 – REVISED JUNE 2016 Product Folder Links: DAC7750 DAC8750 Submit Documentation Feedback Copyright © 2013–2016, Texas Instruments Incorporated Typical Characteristics (continued) at TA = 25°C (unless otherwise noted) RLOAD = 300 Ω 0-mA to 24-mA range Figure 34. IOUT DNL vs Supply (Internal RSET) RLOAD = 300 Ω 0-mA to 24-mA range Figure 35. IOUT DNL vs Supply (External RSET) AVDD = 10 V RLOAD = 300 Ω Figure 36. IOUT Full-Scale Error vs Temperature AVDD = 10 V RLOAD = 300 Ω Figure 37. IOUT Offset Error vs Temperature AVDD = 10 V RLOAD = 300 Ω Figure 38. IOUT Gain Error vs Temperature 33 units shown Figure 39. R3 Resistance vs Temperature 1. Compliance voltage headroom is defined as the drop from AVDD terminal to the IOUT terminal. |
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