DAC8750IPWPR datasheet(34/53 Pages) TI1

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12-/16-Bita__

DAC__a

RSET

12.5 k

HART FSK Input

CAP2

CAP1

AVDD

GND

IOUT

BOOST

R3-SENSE

DAC7750, DAC8750

SBAS538B – DECEMBER 2013 – REVISED JUNE 2016

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Product Folder Links: DAC7750 DAC8750

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Implementing HART in All Current Output Modes

If it is desirable to implement HART irrespective of the RANGE bit settings, there are two ways to do this.

9.1.1.1 Using CAP2 Terminal

The first method of implementing HART is to couple the signal through the CAP2 pin, as illustrated in Figure 60.

Note that this pin is only available in the 40-pin VQFN package

Figure 60. Implementing HART on IOUT Using the CAP2 Terminal

In Figure 60, R3 is nominally 40 Ω, and R2 is dependent on the current output range (set by the RANGE bits),

described as follows:

•

4-mA to 20-mA range: R2 = 2.4 kΩ (typical)

•

0-mA to 20-mA range: R2 = 3 kΩ (typical)

•

0-mA to 24-mA range: R2 = 3.6 kΩ (typical)

The purpose of the 12.5-kΩ resistor is to create a filter when CAP1 and CAP2 are used.

To insert the external HART signal on the CAP2 terminal, an external ac-coupling capacitor is typically connected

to CAP2. The high pass filter 3-dB frequency is determined by the resistive impedance looking into

CAP2 (R2 + 12.5 kΩ) and the coupling-capacitor value. The 3-dB frequency is 1 / (2 × π × [R2 + 12.5 kΩ] ×

[Coupling Capacitor Value]).

When the input HART frequency is greater than the 3-dB frequency, the ac signal is seen at the plus input of

amplifier A2 and is therefore seen across the 40-Ω resistor. To generate a 1-mA signal on the output therefore

requires a 40-mV peak-to-peak signal on CAP2. Because most HART modems do not output a 40-mV signal, a

capacitive divider is used in Figure 60 to attenuate the FSK signal from the modem. In Figure 60, the high-pass

cutoff frequency is 1 / (2 × π × [R2+ 12.5 kΩ] × [C1 + C2]). There is one disadvantage to this approach: if the

AVDD supply is not clean, any ripple on it could couple into the part.

DAC8750IPWPR Datasheet(PDF) 34 Page - Texas Instruments

DAC8750IPWPR Datasheet(HTML) 34 Page - Texas Instruments

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