DAC8750IPWPR datasheet(23/53 Pages) TI1

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Supply (V)

Specified Supply

Voltage Range

No Power-On Reset

Supply Max.

Supply Min.

Power-On Reset

POR Threshold

Undefined

Undefined Operation Threshold

DAC7750, DAC8750

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SBAS538B – DECEMBER 2013 – REVISED JUNE 2016

Product Folder Links: DAC7750 DAC8750

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Feature Description (continued)

8.3.7 Power-On Reset

The DACx750 incorporates two internal POR circuits for the DVDD and AVDD supplies. The DVDD and AVDD

POR signals are ANDed together so that both supplies must be at their minimal specified values for the device to

not be in a reset condition. These POR circuits initialize internal logic and registers, as well as set the analog

outputs to a known state while the device supplies are ramping. All registers are reset to their default values.

Typically the POR function can be ignored, as long as the device supplies power-up and maintains the specified

minimum voltage levels. However, in the case of a supply drop or brownout, the DACx750 can have an internal

POR reset event or lose digital memory integrity. Figure 54 represents the threshold levels for the internal POR

for both the DVDD and AVDD supplies.

Figure 54. Relevant Voltage Levels for POR Circuit

For the DVDD supply, no internal POR occurs for nominal supply operation from 2.7 V (supply min) to 5.5 V

(supply max). For the DVDD supply region between 2.4 V (undefined operation threshold) and 0.8 V (POR

threshold), the internal POR circuit may or may not provide a reset over all temperature conditions. For the

DVDD supply below 0.8 V (POR threshold), the internal POR resets if the supply voltage remains less than 0.8 V

for approximately 1 ms.

For the AVDD supply, no internal POR occurs for nominal supply operation from 10 V (supply min) to 36 V

(supply max). For AVDD supply voltages between 8 V (undefined operation threshold) and 1 V (POR threshold),

the internal POR circuit may or may not provide a reset over all temperature conditions. For the AVDD supply

below 1 V (POR threshold), the internal POR resets if the supply voltage remains less than 1 V for approximately

1 ms. In case the DVDD or AVDD supply drops to a level where the internal POR signal is indeterminate, either

power cycle the device, or toggle the LATCH terminal and then perform a software reset. Both options initialize

the internal circuitry to a known state and provide proper operation.

8.3.8 Alarm Detection

These devices also provide an alarm detection feature. When one or more of following events occur, the ALARM

terminal goes low:

•

The current output load is in open circuit,

•

The voltage at IOUT reaches a level where accuracy of the output current is compromised. This condition is

detected by monitoring internal voltage levels of the IOUT circuitry and is typically below the specified

compliance voltage headroom (defined as the voltage drop between the AVDD and IOUT terminals) minimum

of 2 V,

•

The die temperature exceeds 142°C,

•

The SPI watchdog timer exceeds the timeout period (if enabled), or

•

The SPI frame error CRC check encounters an error (if enabled).

DAC8750IPWPR Datasheet(PDF) 23 Page - Texas Instruments

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