DAC8750IPWPR datasheet(39/53 Pages) TI1

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GND

AVSS

AVDD

Digital I/O

Analog Supply Decoupling

Digital Supply

Decoupling

External RSET

(Optional)

BOOST Configuration

(Optional)

DAC7750, DAC8750

www.ti.com

SBAS538B – DECEMBER 2013 – REVISED JUNE 2016

Product Folder Links: DAC7750 DAC8750

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11 Layout

11.1 Layout Guidelines

To maximize the performance of the DACx750 in any application, good layout practices and proper circuit design

must be followed. A few recommendations specific to the DACx750 are:

1. As is seen in Figure 60, CAP2 is directly connected to the input of the final IOUT amplifier. Any noise or

unwanted ac signal routed near the CAP1 and CAP2 terminals could capacitively couple onto internal nodes

and affect IOUT. Therefore, it is important to avoid routing any digital or HART signal traces over the CAP1

and CAP2 traces.

2. Connect the thermal PAD to the lowest potential in the system.

3. Make sure that AVDD has decoupling capacitors local to the respective terminals.

4. Place the reference capacitor close to the reference input terminal.

5. Avoid routing switching signals near the reference input.

6. For designs that include protection circuits:

(a) Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure

that return current from high-energy transients does not cause damage to sensitive devices.

(b) Use large, wide traces to provide a low-impedance path to divert high-energy transients away from I/O

terminals.

11.2 Layout Example

Figure 65 shows an example layout for the DAC8760 and DAC7760 devices from TIPD153. A similar layout can

be used for the DACx750 with a few modifications to account for pinout differences.

Figure 65. Example Layout

DAC8750IPWPR Datasheet(PDF) 39 Page - Texas Instruments