DAC8750IPWPR datasheet(31/53 Pages) TI1

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SDI

LATCH

SCLK

SDI-B

SDI-A

SDI-C

SDO-C

SDO-B

SDO-A

SDO

DAC7750, DAC8750

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SBAS538B – DECEMBER 2013 – REVISED JUNE 2016

Product Folder Links: DAC7750 DAC8750

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(1)

X denotes don't care bits.

(2)

DAC8750 (16-bit version) shown. DAC7750 (12-bit version) contents are located in DB15:DB4.

For DAC7750, DB3:DB0 are don't care bits when writing and zeros when reading.

(3)

No operation, read operation, and watchdog timer are commands and not registers.

Figure 59. Three DACx750s in Daisy-Chain Mode

Like stand-alone operation, the SPI daisy-chain write operation requires one frame, and the read requires two

frames. The rising edge of SCLK that clocks in the MSB of the input frame marks the beginning of the write

cycle. When the serial transfer to all devices is complete, LATCH is taken high. This action transfers the data

from the SPI shift registers to the device internal register of each DACx750 in the daisy-chain. However, the

number of clocks in each frame in this case depends on the number of devices in the daisy chain. For two

devices, each frame is 48 clocks; the first 24 clocks are for the second DAC and the next 24 bits are for the first

DAC. For a readback, the data are read from the two DACs in the following 48-bit frame; the first 24 clocks are

for the second DAC, and the next 24 clocks are for the first DAC. The input data to the DACs during the second

frame can be another command or NOP. Similar to the two-device case described, for N devices, each frame is

N × 24 clocks, where N is the total number of DACx750s in the chain.

The serial clock can be a continuous or gated clock. A continuous SCLK source can only be used if LATCH is

taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact

number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data.

8.6 Register Maps

Table 11 shows the available registers on the DACx750 devices. See DACx750 Register Descriptions for

descriptions of all DACx750 registers.

Table 11. Command and Register Map

COMMAND

READ AND

WRITE

ACCESS

DATA BITS (DB15:DB0)

15:14

10:9

Control

REXT

OUTEN

SRCLK

SRSTEP

SREN

DCEN

RANGE

Configuration

(1)

CALEN

HARTEN

CRCEN

WDEN

WDPD

DAC Data

(2)

D15:D0

No operation

(3)

—

Read Operation

(3)

—

READ ADDRESS

Reset

RESET

Status

Reserved

CRC-FLT

WD-FLT

I-FLT

SR-ON

T-FLT

DAC Gain

Calibration

(2)

G15:G0, unsigned

DAC Zero

Calibration

(2)

Z15:Z0, signed

Watchdog Timer

(3)

—

DAC8750IPWPR Datasheet(PDF) 31 Page - Texas Instruments

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