DAC8750IPWPR datasheet(25/53 Pages) TI1

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User _ GAIN

CODE _ OUT

CODE •

User _ ZERO

DAC7750, DAC8750

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SBAS538B – DECEMBER 2013 – REVISED JUNE 2016

Product Folder Links: DAC7750 DAC8750

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8.3.11 User Calibration

The device implements a user-calibration function (enabled by the CALEN bit in the Configuration Register) to

trim system gain and zero errors. The DAC output is calibrated according to the value of the gain calibration and

zero calibration registers. The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The

gain register must be programmed to 0x8000 to achieve the default gain of 1 because the power-on value of the

per step. The input data format of the gain register is unsigned straight binary, and the input data format of the

zero register is twos complement. The gain and offset calibration is described by Equation 4.

where

•

CODE is the decimal equivalent of the code loaded to the DAC data register at address 0x01

•

N is the bits of resolution (16 for DAC8750 and 12 for DAC7750)

•

User_ZERO is the signed 16-bit code in the zero register

•

User_GAIN is the unsigned 16-bit code in the gain register

•

CODE_OUT is the decimal equivalent of the code loaded to the DAC (limited between 0x0000 to 0xFFFF for

DAC8750 and 0x000 to 0xFFF for DAC7750)

(4)

This is a purely digital implementation and the output is still limited by the programmed value at both ends of the

current output range (set by the RANGE bits, as described in Setting Current-Output Ranges). In addition, the

correction only makes sense for endpoints inside of the true device end points. To correct more than just the

actual device error, for example a system offset, the valid range for the adjustment changes accordingly and

must be taken into account.

8.3.12 Programmable Slew Rate

The slew rate control feature controls the rate at which the output current changes. With the slew rate control

feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load.

To reduce the slew rate, enable the slew rate control feature through bit 4 of the Control Register. With this

feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a

rate defined by bits [7:5] (SRSTEP) and bits [11:8] (SRCLK) of the Control Register. SRCLK defines the rate at

which the digital slew updates; SRSTEP defines the amount by which the output value changes at each update.

If the DAC data register is read while the DAC output is still changing, the instantaneous value is read. Table 3

lists the slew rate step-size options. Table 4 summarizes the slew rate update clock options.

Table 3. Slew Rate Step-Size (SRSTEP) Options

SRSTEP

STEP SIZE (LSB)

DAC7750

DAC8750

000

0.0625

001

0.125

010

0.125

011

0.5

100

101

110

111

128

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