DAC8750IPWPR datasheet(32/53 Pages) TI1

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DAC7750, DAC8750

SBAS538B – DECEMBER 2013 – REVISED JUNE 2016

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8.6.1 DACx750 Register Descriptions

8.6.1.1 Control Register

The DACx750 control register is written to at address 0x55. Table 12 shows the description for the control

Table 12. Control Register

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB14

Reserved

Reserved. Do not write any value other than zero to these bits.

DB13

REXT

External current setting resistor enable.

DB12

OUTEN

Output enable.

Bit = 1: Output is determined by RANGE bits.

Bit = 0: Output is disabled. IOUT is Hi-Z.

DB11:DB8

SRCLK[3:0]

0000

Slew rate clock control. Ignored when bit SREN = 0.

DB7:DB5

SRSTEP[2:0]

000

Slew rate step size control. Ignored when bit SREN = 0.

DB4

SREN

Slew Rate Enable.

Bit = 1: Slew rate control is enabled, and the ramp speed of the output change is determined

by SRCLK and SRSTEP.

Bit = 0: Slew rate control is disabled. Bits SRCLK and SRSTEP are ignored. The output

changes to the new level immediately.

DB3

DCEN

Daisy-chain enable.

DB2:DB0

RANGE[2:0]

000

Output range bits.

8.6.1.2 Configuration Register

The DACx750 configuration register is written to at address 0x57. Table 13 summarizes the description for the

configuration register bits.

Table 13. Configuration Register

DATA BIT(S)

NAME

DEFAULT

DESCRIPTION

DB15:DB6

Reserved

00 0000 0000

Reserved. Do not write any value other than zero to these bits.

DB5

CALEN

User calibration enable. When user calibration is enabled, the DAC data are

adjusted according to the contents of the gain and zero calibration registers. See

the User Calibration section.

DB4

HARTEN

Enable interface through HART-IN terminal (only valid for IOUT set to 4-mA to

20-mA range through RANGE bits).

Bit = 1: HART signal is connected through internal resistor and modulates output

current.

Bit = 0: HART interface is disabled.

DB3

CRCEN

Enable frame error checking.

DB2

WDEN

Watchdog timer enable.

DB1:DB0

WDPD[1:0]

Watchdog timeout period.

8.6.1.3 DAC Registers

The DAC registers consist of a DAC data register (Table 14), a DAC gain calibration register (Table 15), and a

DAC zero calibration register (Table 16). User calibration as described in the User Calibration section is a feature

that allows for trimming the system gain and zero errors. Table 14 through Table 16 show the DAC8750, 16-bit

version of these registers. The DAC7750 (12-bit version) register contents are located in DB15:DB4. For

DAC7750, DB3:DB0 are don't care bits when writing and zeros when reading.

Table 14. DAC Data Register

DATA BITS

NAME

DEFAULT

DESCRIPTION

DB15:DB0

D15:D0

0x0000

DAC data register. Format is unsigned straight binary.

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