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DAC8750IPWPR Datasheet(PDF) 36 Page - Texas Instruments

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Part # DAC8750IPWPR
Description  DACx750 Single-Channel, 12- and 16-Bit Programmable Current Output Digital-to-Analog Converters for 4-mA to 20-mA Current Loop Applications
PDF  53 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC8750IPWPR Datasheet(HTML) 36 Page - Texas Instruments

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ISO7631
DACX750
IOUT
Current Output
0-20mA, 4-20mA, 0-24mA
+24V
100nF
15
Ÿ
REFIN
REFOUT
GND
HART-IN
HART Signal
FSK 1200-2200Hz
AVDD
DVDD
DVDD-EN
+24V
0.1PF
0.1PF
22PF
100pF
0.1PF
SCLK
DIN
SDO
LATCH
CLR
ALARM
10
NŸ
INC
OUTA
OUTB
VCC2
GND2
0.1PF
0.1PF
ISO7631
INC
OUTA
OUTB
VCC2
GND2
VCC1
GND1
OUTC
INA
INB
VCC1
GND1
OUTC
INA
INB
Digital Controller
GND
VDD
0.1PF
0.1PF
0.1PF
SCLK
MOSI
MISO
/CS
GPIO
GPIO
Isolation
Barrier
+24V Field Supply Input
Field GND
Field
Connections
+24V
Unidirectional
TVS Diode Pair
Copyright © 2016, Texas Instruments Incorporated
36
DAC7750, DAC8750
SBAS538B – DECEMBER 2013 – REVISED JUNE 2016
www.ti.com
Product Folder Links: DAC7750 DAC8750
Submit Documentation Feedback
Copyright © 2013–2016, Texas Instruments Incorporated
9.2 Typical Application
9.2.1 Voltage and Current Output Driver for Factory Automation AND Control, EMC/EMI Protected
Figure 62. DACx750 in an Analog Output (AO) Module
9.2.1.1 Design Requirements
Analog I/O modules are used by programmable logic controllers (PLCs) and distributed control systems (DCSs)
to interface to sensors, actuators, and other field instruments. These modules must meet stringent electrical
specifications for both performance as well as protection. These outputs are typically current loops based on the
4-mA to 20-mA range. Common error budgets accommodate 0.1% full-scale range total unadjusted error (%
FSR TUE) at room temperature. Designs which desire stronger accuracy over temperature frequently implement
calibration. Often times the PLC back-plane provides access to a 12-V to 36-V analog supply from which a
majority of supply voltages are derived.
9.2.1.2 Detailed Design Procedure
Figure 63 illustrates a common generic solution for realizing these desired voltage and current output spans.



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