DAC8750IPWPR datasheet(30/53 Pages) TI1

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DAC7750, DAC8750

SBAS538B – DECEMBER 2013 – REVISED JUNE 2016

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Table 8. Write Address Functions

ADDRESS

BYTE

(HEX)

FUNCTION

No operation (NOP)

Write DAC Data register

Write control register

Write reset register

Write configuration register

Write DAC gain calibration register

Write DAC zero calibration register

Watchdog timer reset

8.5.1.3 Read Operation

A read operation is accomplished when the address byte is 0x02. Follow the read operation with a no-operation

(NOP) command to clock out an addressed register, as shown in Figure 2. To read from a register, the address

byte and data word is as shown in Table 9. The read register value is output MSB first on SDO on successive

falling edges of SCLK.

Table 9. Default SPI Frame for Register Read

ADDRESS BYTE

(HEX)

DATA WORD

BIT 15:BIT 6

BIT 5:BIT 0

X (don't care)

Table 10 shows the register read addresses available on the DACx750 devices.

(1)

X denotes don't care bits.

Table 10. Register Read Address Functions

READ ADDRESS(1)

FUNCTION

XX XX00

Read status register

XX XX01

Read DAC data register

XX XX10

Read control register

00 1011

Read configuration register

01 0011

Read DAC gain calibration register

01 0111

Read DAC zero calibration register

8.5.1.4 Stand-Alone Operation

SCLK can operate in either continuous or burst mode, as long as the LATCH rising edge occurs after the

appropriate number of SCLK cycles. Providing more than or less than 24 SCLK cycles before the rising edge of

LATCH results in incorrect data being programmed into the device registers, and incorrect data sent out on SDO.

The rising edge of SCLK that clocks in the MSB of the 24-bit input frame marks the beginning of the write cycle,

and data are written to the addressed registers on the rising edge of LATCH.

8.5.1.5 Daisy-Chain Operation

For systems that contain multiple DACx750s, use the SDO terminal to daisy-chain several devices. This mode is

useful in reducing the number of serial interface lines in applications that use multiple SPI devices. Daisy-chain

mode is enabled by setting the DCEN bit of the control register to 1. By connecting the SDO of the first device to

the SDI input of the next device in the chain, a multiple-device interface is constructed, as Figure 59 illustrates.

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