TMS320C6745DPTP3 datasheet(79/227 Pages) TI1

79 / 227 page

TMS320C6745, TMS320C6747

www.ti.com

SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014

6.8

General-Purpose Input/Output (GPIO)

The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, a write to an internal register can control the state driven on the output pin.

When configured as an input, the state of the input is detectable by reading the state of an internal

interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.

The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).

The C6745/6747 GPIO peripheral supports the following:

•

Up to 128 Pins on ZKB and up to 109 Pins on PTP package configurable as GPIO

•

External Interrupt and DMA request Capability

–

Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or

falling edges on the pin.

–

The interrupt requests within each bank are combined (logical or) to create eight unique bank level

interrupt requests.

–

The bank level interrupt service routine may poll the INTSTATx register for its bank to determine

which pin(s) have triggered the interrupt.

–

GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62

and 72 respectively

–

Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,

and 29 respectively.

•

Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO

signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section

protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to

anther process during GPIO programming).

•

Separate Input/Output registers

•

Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can

be toggled by direct write to the output register(s).

•

Output register, when read, reflects output drive status. This, in addition to the input register reflecting

pin status and open-drain I/O cell, allows wired logic be implemented.

The memory map for the GPIO registers is shown in Table 6-8. See the TMS320C6745/C6747 DSP

Peripherals Overview Reference Guide. (SPRUFK9) for more details.

6.8.1

GPIO Register Description(s)

Table 6-8. GPIO Registers

BYTE ADDRESS

ACRONYM

0x01E2 6000

REV

Peripheral Revision Register

0x01E2 6004

Reserved

0x01E2 6008

BINTEN

GPIO Interrupt Per-Bank Enable Register

GPIO BANKS 0 AND 1

0x01E2 6010

DIR01

GPIO Banks 0 and 1 Direction Register

0x01E2 6014

OUT_DATA01

GPIO Banks 0 and 1 Output Data Register

0x01E2 6018

SET_DATA01

GPIO Banks 0 and 1 Set Data Register

0x01E2 601C

CLR_DATA01

GPIO Banks 0 and 1 Clear Data Register

0x01E2 6020

IN_DATA01

GPIO Banks 0 and 1 Input Data Register

0x01E2 6024

SET_RIS_TRIG01

GPIO Banks 0 and 1 Set Rising Edge Interrupt Register

0x01E2 6028

CLR_RIS_TRIG01

GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register

0x01E2 602C

SET_FAL_TRIG01

GPIO Banks 0 and 1 Set Falling Edge Interrupt Register

0x01E2 6030

CLR_FAL_TRIG01

GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Links: TMS320C6745 TMS320C6747

TMS320C6745DPTP3 Datasheet(PDF) 79 Page - Texas Instruments

TMS320C6745DPTP3 Datasheet(HTML) 79 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL