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TMS320C6745DPTP3 Datasheet(PDF) 89 Page - Texas Instruments |
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TMS320C6745DPTP3 Datasheet(HTML) 89 Page - Texas Instruments |
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89 / 227 page ![]() EMA_CLK EMA_BA[1:0] EMA_CS[0] EMA_CAS EMA_RAS EMA_WE CLK CE WE EMIFA SDRAM 2Mx16x4 Bank EMA_SDCKE CAS RAS CKE BA[1:0] LDQM UDQM DQ[15:0] A[11:0] EMA_A[12:0] EMA_WE_DQM[0] EMA_WE_DQM[1] EMA_D[15:0] EMA_CS[2] EMA_CS[3] EMA_WAIT EMA_OE GPIO (6Pins) RESET A[0] A[12:1] DQ[15:0] CE WE OE RESET A[18:13] RY/ Y B NOR FLASH 512Kx16 ALE CLE DQ[15:0] CE WE RE RB NAND FLASH 1Gbx16 EMA_A[1] EMA_A[2] ... DVDD RESET TMS320C6745, TMS320C6747 www.ti.com SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014 A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-13. This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to bootload it. Note that this example could also apply to the C6745 device; except only one multiplane NAND could be supported with only EMA_CS[3:2] available. Figure 6-12. C6745/6747 Connection Diagram: SDRAM, NOR, NAND Copyright © 2008–2014, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 89 Submit Documentation Feedback Product Folder Links: TMS320C6745 TMS320C6747 |
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