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TMS320C6745DPTP3 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320C6745DPTP3 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 227 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320C6745, TMS320C6747 www.ti.com SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor 1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor 1.1 Features 1 Bit Multiplies, Four 16 x 16-Bit Multiplies, or • Software Support Eight 8 x 8-Bit Multiplies per Clock Cycle, – TI DSP/BIOS™ and Complex Multiples – Chip Support Library and DSP Library – Instruction Packing Reduces Code Size • 375- and 456-MHz TMS320C674x VLIW DSP – All Instructions Conditional • C674x Instruction Set Features – Hardware Support for Modulo Loop – Superset of the C67x+ and C64x+ ISAs Operation – Up to 3648 MIPS and 2736 MFLOPS C674x – Protected Mode Operation – Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – Exceptions Support for Error Detection and – 8-Bit Overflow Protection Program Redirection – Bit-Field Extract, Set, Clear • 128KB of RAM Shared Memory (TMS320C6747 – Normalization, Saturation, Bit-Counting Only) – Compact 16-Bit Instructions • 3.3-V LVCMOS I/Os (Except for USB Interfaces) • C674x Two-Level Cache Memory Architecture • Two External Memory Interfaces: – 32KB of L1P Program RAM/Cache – EMIFA – 32KB of L1D Data RAM/Cache • NOR (8- or 16-Bit-Wide Data) – 256KB of L2 Unified Mapped RAM/Cache • NAND (8- or 16-Bit-Wide Data) – Flexible RAM/Cache Partition (L1 and L2) • 16-Bit SDRAM with 128-MB Address Space • Enhanced Direct Memory Access Controller 3 (TMS320C6747 Only) (EDMA3): – EMIFB – 2 Transfer Controllers • 32-Bit or 16-Bit SDRAM with 256-MB – 32 Independent DMA Channels Address Space (TMS320C6747) – 8 Quick DMA Channels • 16-Bit SDRAM with 128-MB Address Space (TMS320C6745) – Programmable Transfer Burst Size • Three Configurable 16550-Type UART Modules: • TMS320C674x Fixed- and Floating-Point VLIW DSP Core – UART0 with Modem Control Signals – Load-Store Architecture with Nonaligned – Autoflow Control Signals (CTS, RTS) on UART0 Support Only – 64 General-Purpose Registers (32-Bit) – 16-Byte FIFO – Six ALU (32- and 40-Bit) Functional Units – 16x or 13x Oversampling Option • Supports 32-Bit Integer, SP (IEEE Single • LCD Controller (TMS320C6747 Only) Precision/32-Bit) and DP (IEEE Double • Two Serial Peripheral Interfaces (SPIs) Each with Precision/64-Bit) Floating Point One Chip Select • Supports up to Four SP Additions Per Clock, • Multimedia Card (MMC)/Secure Digital (SD) Card Four DP Additions Every 2 Clocks Interface with Secure Data I/O (SDIO) • Supports up to Two Floating-Point (SP or • Two Master and Slave Inter-Integrated Circuit (I2C DP) Reciprocal Approximation (RCPxP) and Bus™) Square-Root Reciprocal Approximation • One Host-Port Interface (HPI) with 16-Bit-Wide (RSQRxP) Operations Per Cycle Muxed Address/Data Bus for High Bandwidth – Two Multiply Functional Units (TMS320C6747 Only) • Mixed-Precision IEEE Floating Point Multiply • Programmable Real-Time Unit Subsystem Supported up to: (PRUSS) – 2 SP x SP -> SP Per Clock – Two Independent Programmable Realtime Unit – 2 SP x SP -> DP Every Two Clocks (PRU) Cores – 2 SP x DP -> DP Every Three Clocks • 32-Bit Load and Store RISC Architecture – 2 DP x DP -> DP Every Four Clocks • 4KB of Instruction RAM per Core • Fixed-Point Multiply Supports Two 32 x 32- • 512 Bytes of Data RAM per Core 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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