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TMS320C6745DPTP3 Datasheet(PDF) 94 Page - Texas Instruments |
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TMS320C6745DPTP3 Datasheet(HTML) 94 Page - Texas Instruments |
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94 / 227 page  TMS320C6745, TMS320C6747 SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014 www.ti.com Table 6-21. EMIFA Asynchronous Memory Timing Requirements(1) No. PARAMETER MIN NOM MAX UNIT READS and WRITES E tc(CLK) Cycle time, EMIFA module clock 10 ns 2 tw(EM_WAIT) Pulse duration, EM_WAIT assertion and deassertion 2E ns READS 12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 3 ns 13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 0 ns 14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAIT asserted before end of Strobe Phase(2) 4E+3 ns WRITES 28 tsu (EMWEL-EMWAIT) Setup Time, EM_WAIT asserted before end of Strobe Phase (2) 4E+3 ns (1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns. (2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended wait states. Figure 6-18 and Figure 6-19 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. Table 6-22. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3) No. PARAMETER MIN NOM MAX UNIT READS and WRITES 1 td(TURNAROUND) Turn around time (TA)*E - 3 (TA)*E (TA)*E + 3 ns READS (RS+RST+RH)*E (RS+RST+RH)*E EMIF read cycle time (EW = 0) (RS+RST+RH)*E ns - 3 + 3 3 tc(EMRCYCLE) (RS+RST+RH+E (RS+RST+RH+EWC (RS+RST+RH+E EMIF read cycle time (EW = 1) ns WC)*E - 3 )*E WC)*E + 3 Output setup time, EMA_CE[5:2] low to (RS)*E-3 (RS)*E (RS)*E+3 ns EMA_OE low (SS = 0) 4 tsu(EMCEL-EMOEL) Output setup time, EMA_CE[5:2] low to -3 0 +3 ns EMA_OE low (SS = 1) Output hold time, EMA_OE high to (RH)*E - 3 (RH)*E (RH)*E + 3 ns EMA_CE[5:2] high (SS = 0) 5 th(EMOEH-EMCEH) Output hold time, EMA_OE high to -3 0 +3 ns EMA_CE[5:2] high (SS = 1) Output setup time, EMA_BA[1:0] valid to 6 tsu(EMBAV-EMOEL) (RS)*E-3 (RS)*E (RS)*E+3 ns EMA_OE low Output hold time, EMA_OE high to 7 th(EMOEH-EMBAIV) (RH)*E-3 (RH)*E (RH)*E+3 ns EMA_BA[1:0] invalid Output setup time, EMA_A[13:0] valid to 8 tsu(EMBAV-EMOEL) (RS)*E-3 (RS)*E (RS)*E+3 ns EMA_OE low Output hold time, EMA_OE high to 9 th(EMOEH-EMAIV) (RH)*E-3 (RH)*E (RH)*E+3 ns EMA_A[13:0] invalid EMA_OE active low width (EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns 10 tw(EMOEL) EMA_OE active low width (EW = 1) (RST+EWC)*E-3 (RST+EWC)*E (RST+EWC)*E+3 ns td(EMWAITH- Delay time from EMA_WAIT deasserted to 11 3E-3 4E 4E+3 ns EMOEH) EMA_OE high WRITES (1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold, MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1], WH[8-1], and MEW[1-256]. (2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when SYSCLK3 is selected and set to 100MHz, E=10ns. (3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. 94 Peripheral Information and Electrical Specifications Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320C6745 TMS320C6747 |
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