TMS320C6745DPTP3 datasheet(98/227 Pages) TI1

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EMB_CS

EMB_CAS

EMB_RAS

EMB_WE

EMB_CLK

EMB_SDCKE

EMB_BA[1:0]

EMB_A[x:0]

EMB_D[x:0]

EMB_WE_DQM[x:0]

SDRAM

Interface

Cmd/Write

FIFO

Registers

Read

FIFO

Crossbar

EMIFB

Master

Peripherals

(USB, UHPI...)

EDMA

CPU

MPU2

TMS320C6745, TMS320C6747

SPRS377F – SEPTEMBER 2008 – REVISED JUNE 2014

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6.11 External Memory Interface B (EMIFB)

Figure 6-20 illustrates a high-level view of the EMIFB and its connections within the device. Multiple

requesters have access to EMIFB through a switched central resource (indicated as crossbar in the

figure). The EMIFB implements a split transaction internal bus, allowing concurrence between reads and

writes from the various requesters.

Figure 6-20. EMIFB Functional Block Diagram

EMIFB supports a 3.3V LVCMOS Interface.

6.11.1 EMIFB SDRAM Loading Limitations

EMIFB supports SDRAM up to 152MHz with up to two SDRAM or asynchronous memory loads. Additional

loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by

board simulation using IBIS models.

Peripheral Information and Electrical Specifications

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TMS320C6745DPTP3 Datasheet(PDF) 98 Page - Texas Instruments

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