MT9072AB datasheet(42/275 Pages) ZARLINK

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MT9072

Data Sheet

Zarlink Semiconductor Inc.

3.2

T1 Interface to the Physical Layer Device

Control bits in the Line Interface and Coding word (address Y01) determine the format of the PCM24 transmit and

receive signals. Three physical interface formats are provided including RZ dual rail, NRZ dual rail and NRZ single

rail.

The detailed timing diagrams are presented in Figures 45 to Figures 48.

RZ Dual Rail - On the Transmit side the pulse width is approximately half the duration of the PCM24 bit cell

centered around the falling edge of TXCL. On the receive side RPOS and RNEG are sampled on the falling edge of

EXCLi. Note that the CLKE bit in register Y01 (selectable for edge sampling) has no effect in RZ mode.

NRZ Dual Rail - With this format, pulses are present for the full bit cell, which allows the set-up and hold times to be

easily met. For the receiver the sampling point can be the rising edge or the falling edge of the EXCLi clock,

depending on the CLKE bit in Register Y01. The transmitted data can be output either on the rising or falling edge

of TXCL selected by the CLKE bit. TXCL is an input in T1 mode and an output in E1 mode.

NRZ Single Rail - This NRZ format is not dual rail, and therefore, only requires a single output line and a single

input line (i.e., TPOS and RPOS). The CLKE bit in Register Y01 controls the TXCL clock edge and the EXCLi

sampling edge.

3.3

T1 Line Coding

B8ZS (zero code substitution) is selectable globally for both the transmit and receive path (register Y01). Jammed

bit 7, GTE, DDS or BELL zero code suppression are also available for the transmitter and receiver(register Y01).

Different schemes for provision of ones density can be selected with bits ZCS2:0 (registers Y01). GTE suppression

is achieved by replacing the LSB of zero bytes by a one except for the signaling frame. DDS suppression is

replacement of zero byte by 10011000. Bell code suppression is replacement of bit 1(second bit after LSB) of a

zero byte. Jammed bit seven selection will replace the LSB of each channel with a ’1’.

3.4

T1 Pulse Density

Bit 4 of address Y10 (PDV) toggles if the receive data fails to meet ones density requirements. It will toggle upon

detection of 16 consecutive zeros in the line data, or if there are fewer than N ones in a window of 8(N+1) bits -

where N = 1 to 23.

The transmit T1 data is monitored and if the 12.5% density requirement is not met over a maximum 192 bit window

a one is inserted in a non-framing bit. The window and PDV criteria is the same as the received PDV.

PCM24 Channels

bit

56789

ST-BUS Channels

(DSTi/o)

Bit

456789

PCM24 Channels

ST-BUS Channels

(DSTi/o)

Table 3 - ST-BUS vs. PCM24 to Channel Relationship for IMA DST Streams (T1)

MT9072AB Datasheet(PDF) 42 Page - Zarlink Semiconductor Inc

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