MT9072AB datasheet(90/275 Pages) ZARLINK

90 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

14.1.4

T1 Pseudo-Random Bit Sequence (PRBS) Testing

The MT9072 includes both a pseudo random bit sequence (PRBS) generator of type (215-1), and a reverse PRBS

generator (decoder), which operates on a bit sequence, and determines if it matches the transmitted PRBS type

(215-1). Bits which don’t match are counted by an internal error counter. This provides for powerful system

debugging and testing without additional external hardware.

If control bit ADSEQ (register address Y01) is zero, any transmit (internal DSTi) timeslot or combination of transmit

timeslots may be connected to the PRBS generator. Timeslot n is selected by setting the TTSTn bit in the Timeslot

n Control Register (address Y90-YA7), where n is 0 to 23. Any data sent on DSTi is overwritten on the selected

timeslots before being output to TPOS/TNEG.

Similarly, if control bit ADSEQ is zero, any receive timeslot or combination of receive timeslots may be connected to

the PRBS decoder. Timeslot n is selected by setting the RRSTn bit in the Timeslot n Control Register (register

address Y90-YA7), where n is 0 to 23.

PRBS data is distributed to the transmit channels sequentially one byte at a time. Consequently, the data received

must be in the same order that it was sent, in order for the PRBS decoder to correctly operate on the data.

If one channel is tested at a time, then the PRBS transmit timeslot does not have to match the PRBS receive

timeslot. However, if more than one channel is tested, then the number of transmit timeslots must match the

number of receive timeslots, and the order of the transmit timeslots must match the order of the receive timeslots.

This will ensure that the sequential data bytes received by the PRBS decoder are in the correct order.

Consequently, particular care must be taken when using an external loopback where the channel order may be

reversed, or where the data has passed through a digital switch which doesn’t buffer all channels to the same

degree.

The PRBS decoder must have sufficient data pass through it before it begins to operate correctly, therefore, the

errors generated by the decoder immediately following start-up should be ignored.

If the PRBS testing is performed in an external loop around using Timeslot Control, then both Timeslot Control bits

TTSTn and RRSTn should also be set.

Address

Description

Y01

Line Interface and Coding

ADSEQ bit chooses between Milliwatt test sequence and

transmitted PRBS test sequence.

Y90-YA7

Per Channel Control

If TTST is set for any channel, the test sequence will be

transmitted on that DS1 timeslot. If RRST is set for any channel,

the test sequence will be expected on the receivePCM24 slot.

Y15

PRBS Error Counter and CRC

Multiframe Counter for PRBS

The PRBS Error Counter contains error count on the received

PRBS sequence.

Y34

Receive Sync Interrupt Status

PRBSOI will indicate an overflow on the PRBS Error Counter.

Y44

Receive Sync Interrupt Mask

PRBSOIM is the mask for PRBSOI.

Table 44 - Registers Related to PRBS Testing (T1)

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