MT9072AB datasheet(51/275 Pages) ZARLINK

51 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

The submultiframe is then transmitted and, at the far end, the same process occurs. That is, a CRC-4 remainder is

generated for each received submultiframe. These bits are compared with the bits received in position one of the

four FASs of the next received submultiframe. This process takes place in both directions of transmission.

When more than 914 CRC-4 errors (out of a possible 1000) are counted in a one second interval, the framing

algorithm will force a search for a new basic frame alignment if automatic CRC-4 interworking is not invoked.

The result of the comparison of the received CRC-4 remainder with the locally generated remainder will be

transported to the far end by the E-bits. Therefore, if E1 = 0, a CRC-4 error was discovered in a submultiframe 1

received at the far end; and if E2 = 0, a CRC-4 error was discovered in a submultiframe 2 received at the far end.

No submultiframe sequence numbers or re-transmission capabilities are supported with layer 1 PCM30 protocol.

See ITU-T G.704 and G.706 for more details on the operation of CRC-4 and E-bits.

5.2.2.1

E1 Automatic CRC-4 Interworking

When control bit AUTC (register address Y00) is set to zero, the MT9072 framing algorithm supports automatic

interworking of interfaces with and without CRC-4 processing capabilities. That is, if an interface with CRC-4

capability, achieves valid basic frame alignment, but does not achieve CRC-4 multiframe alignment by the end of a

predefined period, the distant end is considered to be a non-CRC-4 interface. When the distant end is a non-CRC-4

interface, the near end automatically suspends receive CRC-4 functions, continues to transmit CRC-4 data to the

distant end with its E-bits set to zero, and provides a status indication. Naturally, if the distant end initially achieves

CRC-4 synchronization, CRC-4 processing will be carried out by both ends.

When control bit AUTC is one, Automatic CRC-4 Interworking is deactivated. In this case, if the Automatic Remote

Alarm Indication (RAI) Operation (ARAI) control bit (register address Y00) is low, and if CRC-4 multiframe

alignment is not found in 400 msec, then the transmit Remote Alarm Indication (RAI) (bit 3 (A) of the transmit

NFAS) will be continuously high until CRC-4 multiframe alignment is achieved.

The TE control bit (register address Y00) for transmit E bits will have the same function in both states of AUTC.

That is, when CRC-4 synchronization is not achieved the state of the transmit E-bits will be the same as the state of

the TE control bit. When CRC-4 synchronization is achieved the transmit E-bits will function as per ITU-T G.704 as

described in the previous section. Table 13 outlines the operation of the AUTC, ARAI and TALM control bits of the

MT9072.

MT9072AB Datasheet(PDF) 51 Page - Zarlink Semiconductor Inc