MT9072AB datasheet(59/275 Pages) ZARLINK

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MT9072

Data Sheet

Zarlink Semiconductor Inc.

7.2

E1 Data Link (DL) Operation

Table 12 shows the contents of the transmit and receive Frame Alignment Signals (FAS) and Non-frame Alignment

Signals (NFAS) of timeslot zero of a PCM30 signal. Even numbered frames (CRC Frame # 0, 2, 4,...) are FASs and

odd numbered frames (CRC Frame # 1, 3, 5,...) are NFASs. The bits of each channel are numbered 1 to 8, with bit

1 being the most significant and bit 8 the least significant. The Data Link (DL) bits, also referred to as National bits,

are the Sa4, Sa5, Sa6, Sa7 and Sa8 bits of the PCM30 timeslot zero NFAS frames. Any number and combination

of these bits may be used for the transport of maintenance and performance monitoring information across the

PCM30 link. The DataLink in controlled by the address Y06 and Y08.

The received Data Link bits are always sent to the DataLink Pins and the National bit buffers(YC0-YC4).

The Data Link (DL) bits (Sa4~Sa8) of the PCM30 timeslot zero NFAS frames can be accessed by the MT9072 in the

following four ways:

• External serial port pins. Hence the user can use pins (TxDL and TxDLC) for transmit data link access and

RxDL and RXDLC for receive data link access

•

Micro port access which would use Transmit 5 bit register (TNU4-8 address YB0 to YB4). For the receiver

Receive 5 bit register (RNU4-8 address YC0-YC4).

• ST-BUS access Transmit ST-BUS (DSTi timeslot 0) enabled by transparent mode

• On board HDLC for Timeslot 0

Note: that the user can source different Sa bits from a combination of the above 4 methods. For instance the Sa4

bit could be sourced from the External Serial Port and Sa5 to Sa8 from the micro port register (TNU5-8 address YB1

to YB4).

The registers related to the configuration control and status of the data link are shown in Table 17.

Address

Description

Y00

Alarm and Framing Control

The Data Link is not supported in the IMA mode.

Y06

HDLC and CCS ST-BUS

control register

The bit HPSEL has to be 0 if the internal HDLC is to be used for the

Data Link.

Y08

Data Link Control Register

This register determines the source of the Sa bits which can be micro

port,HDLC, data link pins or ST-BUS. This register is also used to

control the data link pins Txdl and Rxdl.

Y13

NFAS and FAS status

The national use bits RNU can be read from this status register.

Y26

CAS, National, CRC-4

Latched Status

The Sa bit latched values can be read from this register, SA5VL,

SA6NL etc.

Y36

CAS, National, CRC-4

Interrupt Status

The Sa bit interrupt values can be read from this register, SA5VI,

SA6NI etc.

Y46

CAS, National, CRC-4

Interrupt Mask

These are the mask bits for Y36.

YB0-YB4 Transmit National Bits

Transmit national bits used for sending

Sa bits(SA4 to SA8).

YC0-YC4 Receive national bit

Receive National bits(SA4 to SA8)

Table 17 - Data Link and Sa Bits Configuration and Status Registers (E1)

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