MT9072AB datasheet(70/275 Pages) ZARLINK

70 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

8.2.4

E1 Common Channel Signaling (CCS) Receive from PCM30 to CSTo and DSTo

The CSIG control bit (register address Y03) must be set to one for Common Channel signaling (CCS) operation.

CCS on the receive PCM30 link (bit positions one to eight of timeslots 15, 16 and/or 31 of every frame) is sourced

to the ST-BUS DSTo stream and may also be sourced to the ST-BUS CSTo stream. If the TS15E, TS16E & TS31E

control bits (register address Y06) are zero, the receive data will be sourced to the ST-BUS DSTo stream only,

timeslots 15, 16 and 31. If these bits are one, then the signaling data will be sourced to both the DSTo stream and

the ST-BUS CSTo stream. Note that any combination of the TS15E, TS16E & TS31E control bits (register address

Y06) may be enabled. The CSTo destination timeslots for the receive PCM30 timeslots 15, 16 and 31, are

determined respectively by the 15C4-15C0, 16C4-31C0 and 31C4-31C0 (register address Y07) programming bits.

Table 29 shows the detailed bit mapping of CSTo timeslots from receive PCM30 frames. Table 30 shows the

detailed bit mapping of DSTo timeslots from receive PCM30 frames.

ST-BUS CSTo

PCM30 Receive

CRC-4

Frame

Timeslot

Data Bits (B7-B0)

Timeslot

CRC-4

Frame

Data Bits (B1-B8)

all

Any one of 32

n + m(0 to 31)

P1, P2, P3, P4, P5, P6, P7, P8

all

P1, P2, P3, P4, P5, P6, P7, P8

all

Any one of 32

n + m(0 to 31)

P1, P2, P3, P4, P5, P6, P7, P8

all

P1, P2, P3, P4, P5, P6, P7, P8

all

Any one of 32

n + m(0 to 31)

P1, P2, P3, P4, P5, P6, P7, P8

all

P1, P2, P3, P4, P5, P6, P7, P8

Note 1. For 2.048 Mbit/s operation, m=1 and n=0.

Note 2. For 8.192 Mbit/s operation, m=4 and n =0,1,2,3 where n corresponds to the framer number (i.e., n=0=framer 0... n=3= framer

Note 3. For these functions to be valid, CCS mode must be selected (CSIG=1 register address Y03) and CSTo ST-BUS mode must

be selected (TS15E=1, TS16E=1 & TS31E=1 register address Y06) and the preferred destination CSTo timeslot should be selected

(15C4-0, 16C4-0 & 31C4-0 register address Y07).

Table 29 - Receive PCM30 CCS to ST-BUS 2.048 Mbit/s or 8.192 Mbit/s CSTo (E1)

ST-BUS DSTo

PCM30 Receive

CRC-4

Frame

Timeslot

Data Bits (B7-B0)

Timeslot

CRC-4

Frame

Data Bits (B1-B8)

all

n + m(15) P1, P2, P3, P4, P5, P6, P7, P8

all

P1, P2, P3, P4, P5, P6, P7, P8

all

n + m(16) P1, P2, P3, P4, P5, P6, P7, P8

all

P1, P2, P3, P4, P5, P6, P7, P8

all

n + m(31) P1, P2, P3, P4, P5, P6, P7, P8

all

P1, P2, P3, P4, P5, P6, P7, P8

Note 1. For 2.048 Mbit/s operation, m=1 and n=0.

Note 2. For 8.192 Mbit/s operation, m=4 and n =0,1,2,3 where n corresponds to the framer number (i.e., n=0=framer 0... n=3= framer

Note 3. For these functions to be valid, CCS mode must be selected (CSIG=1 register address Y03).

Table 30 - Receive PCM30 CCS to ST-BUS 2.048 Mbit/s or 8.192 Mbit/s DSTo (E1)

MT9072AB Datasheet(PDF) 70 Page - Zarlink Semiconductor Inc

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